Presentation on theme: "Maciej Gołaszewski Tutor: Tadeusz Sondej, PhD Design and implementation of softcore dual processor system on single chip FPGA Design and implementation."— Presentation transcript:
Maciej Gołaszewski Tutor: Tadeusz Sondej, PhD Design and implementation of softcore dual processor system on single chip FPGA Design and implementation of softcore dual processor system on single chip FPGA Military University of Technology Faculty of Electronics Institute of Telecommunication
Multiprocessor SoCs in FPGA Processor core available as IP-Core. Described in Hardware Description Language (HDL) like VHDL or Verilog. Softcore processor – Examples: NIOS II from Altera, MicroBlaze form Xilinx SoC – integration of main system elements like microprocessor, timers, registers, memory controllers or communication modules in programmable device (FPGA ) FPGA – Field Programmable Gate Array registers
Processor communication Shared memory (SM) all processors have common address space processors can have own local memory (M) to communicate processors modify data in shared memory Message passing processors have separate address space communication is realized by sending messages processors are directly connected
Resource sharing only one of the processors should use the shared resource at the same time to restrict access to shared resource should be used a semaphore Shared memory should be accessed only after successful acquiring of the semaphore
Dual processor system design System tasks: control the time-to- digital converter in FPGA Statistical computation during time intervals measurements Measurement control via Internet connection communication processor computing processor
Time-to-digital converter 32 binary counters counting periods of 16-phase clock of the 400 MHz frequency (both edges of clock are active) equivalent of a single clock signal of 12.8 GHz frequency provides 78 ps resolution in a single stage interpolation measurement range 164 μs can be easily extended
System hardware overview communication processor computing processor FPGA device: Stratix II EP2S60 (Altera)
Hardware implementation Nios II Developement Kit Stratix II Edition FPGA device: Stratix II EP2S60 (Altera) Flash 16MB DDR SDRAM 32MB SSRAM 2MB UARTEthernetJTAG LEDs Push buttons prototype connectors
Software TCP/IP stack implemantation from InterNiche – NicheStack Real-time operating system (RTOS) for embedded devices – µC/OS-II Multithreaded application Code optimized for statistical computation Time-to-digital converter software drivers Single threaded application
Host PC application Programming language: JAVA Measurement control via Internet connection. Measurement result display. Measurement series histogram presentation.
Conclusion Resource2uP System + Timer Counter Available in Stratix II ALUT5 1206 36448 352 Registers3 3924 22848 352 DSP blocks16 288 Memory bits126 464 2 544 192 PLL’s156 FPGA resource utilization Small resource utilization – 13% of Stratix II EPS2S60. System clock – 100 MHz Computing power of one processor is reserved only for statistical computation. Measurement control via Internet connection.
Maciej Gołaszewski Thank you for your attention