1. Functional Timing Analysis Made Fast and General Presenter: Yi-Ting Chung Advisor: Jie-Hong Roland Jiang 03/09/2012 Graduate Institute of Electronics Engineering, National Taiwan University, Taiwan (ROC)

2. Outline 2 Introduction Preliminaries TCF Construction Algorithms Experimental Results Conclusions And Future Work References Circuit Model Sensitization Criteria Satisfiability of Timing Requirement TCF without 0/1-Specificity TCF with 0/1Specificity Comparison on TCF Formulas TCF Equivalence Reduction Delay Computation Critical Region Identification 2

3. 3 Introduction In modern synthesis flow of very large scale integration (VLSI) design, timing analysis is essential in – Identifying timing critical regions for re-synthesis – Determining operable clock frequencies – Avoiding wasteful over-optimization and thus accelerating design closure in meeting stringent timing constraints 1 Combinational circuit Critical region FFs Lower bound of clock period

4. 4 Introduction Timing analysis has two main approaches – Static timing analysis (STA) – Functional timing analysis (FTA) 2 abab Use topological order Pro: linear-time complexity Con: may overestimate delay STA Assume under unit delay model 1 2 1 4 3 FTA Identify false critical paths Pro: accurate Con: NP-hard Delay = 4 abab Delay = 2

5. 5 Introduction We focus on the delay-dependent FTA, identifying true and false paths with respect to some timing library – Delay-independent FTA is incomplete in that not every delay path can be concluded true or false regardless of arbitrary delay assignments 3

6. 6 Introduction We use satisability(SAT)-based computation engine – Reason: clean separation between timed characteristic function (TCF) construction and SAT solving – Challenge: massive numbers of variables and clauses when translating a complex TCF into a conjunctive normal form (CNF) formula for SAT solving – Goal: to improve the efficiency of TCF representation 4

7. Floating-mode operation – Signals are of unknown initial values and stablize to their final values induced by truth assignments on the PIs For a gate f: – v i (controlling value of gate input g i ): the value of f can be determined by g i with v i Some complex gates have no controlling values… – C 1 : the set of primes of f { ab, a’b’d’} – C 0 : the set of primes of f ’ { ab’, a’b, a’d} – Controlling cube: a truth assignment that determines f regardless of other inputs ab – Controlling cube set: C = C 1 + C 0 – minterms { ab, ab’, a’b, a’d} 7 Preliminarie s v1 = 0 v2 = 0 d \ab00011110 01010 10010

8. Timed characteristic function (TCF) – the set of PI assignments that makes the output value of f change from unknown to its final value at a specific timing requirement. – is satisable if there exists some PI assignments to make f stablize __________ than time t no earlier earlier no later later – 0/1-specify TCF: specify the final value of f 8 What Is TCF PIs make f = 1 before time t

9. t TCF … TCF Equivalence Table 9 t TCF … a 1 =min arrival time of f a m =max arrival time of f no earlier earlier no later later

10. TCF can be used to find circuit delay by formulating the problem as searching the maximum D such that the formula or is satisfiable. 10 Find Circuit Delay by TCF Topological max delay Searching order D UNSAT SAT D UNSAT SAT Functional max delay UNSAT: cannot find a PO stablizing later than time D Need more test ! no/ earlier no/ later (1)(2)

11. Algorithm We choose no earlier/earlier TCF to compute delay – Search the max D such that or is satisfiable. For each D, – Construct these TCFs recursively from POs to PIs – Convert them to CNF – SAT solving Satisfiable: functional max delay is D Unsatisfiable: reduce D and try again

12. d = 1 12 Delay Model Fall/rise-combined delay model – Unit delay model – fanout delay model Fall/rise-separate delay model – TSMC 0.18um delay model d = 1.4 df = 0.23 dr = 0.27

13. formula [1] (for simple gate only) Our formula Example: construct Simple TCF Formula 13 abab f (3) a b (4) 13 clauses + 3 extra variables 3 clauses Target: to build (3) (4)

14. Assume delay of INV = 1, delay of AND = 3 Compute A={topological arrival time list} Search max D such that is satisfiable. (D = 7 initially) The functional max delay is 7, sensitized by “a=1, b=1” Example 14 e f abab {0} {1} {3, 4} {3, 6, 7} d 00 (by equivalence table) Must be 1 00 1 Satisfiable! Combined delay model

15. Prior formula [2] (for simple gate only) Prior formula [3] Our formulas 0/1-Specify TCF Formula 15 Target: to build (6) (5) AND OR v={0,1} k=0 if Lit(gi)=gi’ K=1 if Lit(gi)=gi (7)(8)

16. Problem – Topological arrival time lists are not efficient for fall/rise- separate delay models. – INV: falling delay d f = 12, rising delay d r = 21 – AND: falling delay d f = 23, rising delay d r = 27 – Compute A Example 16 e f abab {0} {12, 21} {23, 27, 35, 39, 44, 48} {23, 27, 46, 50, 54, 58, 62, 66, 67, 71, 75, 79} d Many arrival times… UNSAT Separate delay model

17. Each gate f has two arrival time lists A 0 (f) = {Falling arrival time list} (arrival times for f = 0) A 1 (f) = {Rising arrival time list} (arrival times for f = 1) Define the output controlling value of simple gate f to be c o. i.e. the value of f is determined from unknown to c o by an input g i with input controlling value c i. Define the output non-controlling value of f to be nc o. i.e. the value of f is determined from unknown to nc o by every input g i with input non-controlling value nc i. – Ex. c o = 1, c 1 = 0, c 2 = 1 nc o = 0, nc 1 = 1, nc 2 = 0 0/1-Separate Arrival Time List 17 g1g2g1g2 f 1

18. Compute fall/rise-separate arrival time lists – Output controlling value must be sensitized by an input controlling value. 18 g1g2g1g2 f A 0 (g 1 ) = {1, 5} A 0 (g 2 ) = {2, 5} A 0 (f) = {24, 25, 28} d 0 = 23 Linear time complexity 2 0/1-Separate Arrival Time List

19. Compute fall/rise-separate arrival time lists – Output non-controlling value must not be sensitized by an earlier input non-controlling value. 3 19 Before p, at least one fanin is not ready to input controlling value, so f cannot be determined yet. g1g2g1g2 f A 1 (g 1 ) = {1, 3, 5} A 1 (g 2 ) = {4, 6} A 1 (f) = {28, 30, 31, 32, 33} d 1 = 27 p = 4  arrival times 1 and 3 need not propagate to FO PS. Also work for XOR gates 0/1-Separate Arrival Time List

20. Before separation of 0/1: After separation of 0/1: Comparison 20 e f abab A(a)={0} A(b)={0} {12, 21} {23, 27, 35, 39, 44, 48} {23, 27, 46, 50, 54, 58, 62, 66, 67, 71, 75, 79} d e f abab A 0 (a)={0} A 1 (a)={0} d A 0 (b)={0} A 1 (b)={0} {12} {21} {23, 35} {42} {23, 46, 58} {75} Many redundant arrival times INV: d f = 12, d r = 21 AND: d f = 23, d r = 27 Equivalence look- up table is more efficient

21. Compute 0/1-separate arrival time lists – D = 75 – D = 58 21 e f abab A 0 (a)={0} A 1 (a)={0} d A 0 (b)={0} A 1 (b)={0} {12} {21} INV: d f = 12, d r = 21 AND: d f = 23, d r = 27 {23, 35} {42} {23, 46, 58} {75} 01 0 UNSAT Remove {75} How to build gate function efficiently? 0 10 SAT when D=58 Return “a=1, b=1” Example Separate delay model

22. Directly transform Use implication when only need f or f’, remove all BUF/INV CNF of Gate Function 22 Replace d by b’ directly a a’a a Example

23. 1. Fall/rise-separate arrival time lists  add the concept of p 2. Build gate functions  remove all BUFF and INV 3. Change TCF formulas of [1] to implication form SAT solver time (s): Experimental Results 23 DelayCircuit[1]New 123OurNew12 Unit b181.721.150.290.18 b1911.506.980.760.53 leon3mp1222972500.790.37 TSMC leon3130.698.112.7310.96 leon3mp603.0910750.2235.27 netcard92964993809045683803 73843 without New3 New

24. Accelerate the program Use X(f, =t)? Is the critical region computed by combined TCF formula useful for a separate delay model? Can deal with incremental delay change? [1] L. Silva, J. Marques-Silva, L. Silveira, and K. Sakallah. Satisability models and algorithms for circuit delay computation. ACM Trans. on Design Automation of Electronic Systems, 7(1): 137-158, Jan. 2002. [2] Y.-M. Kuo, Y.-L. Chang, and S.-C. Chang. Efficient Boolean characteristic function for timied automatic test pattern generation. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 28(3): 417-425, March 2009. [3] P. McGeer, A. Saldanha, R. Brayton, and A. Sangiovanni-Vincentelli, Logic Synthesis and Optimization, ch. Delay Models and Exact Timing Analysis, pp. 167189. Kluwer Academic Publishers, 1993. Future Work & References 24 Thank You!