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1 Recursive Learning Madhurima Maddela. ELEC 7250 04/26/052 Decision Tree Traditionally used to branch and bound in the search space to generate test.

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Presentation on theme: "1 Recursive Learning Madhurima Maddela. ELEC 7250 04/26/052 Decision Tree Traditionally used to branch and bound in the search space to generate test."— Presentation transcript:

1 1 Recursive Learning Madhurima Maddela

2 ELEC 7250 04/26/052 Decision Tree Traditionally used to branch and bound in the search space to generate test vectors Inefficient for hard-to-detect and redundant faults Solution! Recursive learning H. Fujiwara, T. Shimono, "On the Acceleration of Test Generation Algorithms", 13th Intl. Symp. on Fault TolerantComp., pp. 98-105, 1983.

3 ELEC 7250 04/26/053 The concept Decision tree looks for one successful solution Recursive learning looks for necessary conditions to purge the non-solution area Generates all the necessary assignments for a given condition, very effective around indirect implications. Doesn’t retrace the same path twice, backtracks can be completely avoided Can be called recursively, hence accounts for completeness. W. Kunz, “HANNIBAL: An Efficient Tool for Logic verification Based on Recursive Learning,” ICCAD, pp. 538-543, 1993. W. Kunz and D. K. Pradhan, “Recursive Learning Technique and Applications to CAD,” US Patent Application No. 08/263721

4 ELEC 7250 04/26/054 Fault Propagation using Recursive Learning Learning Level 0 (generally valid signal values) F 0 = {b,e,g,h} Enter learning -> n =0 Learning Level 1 D- frontier signal b: 1. sensitization: successor of b: => j = D, c = 1 successor of j: => s = D, (unjust.) Enter next recursion -> 1. sensitization failed D- frontier signal e: 2. sensitization: successor of e: => k = D, d=0 successor of k: => s = D (unjust.) Enter next recursion -> 2. sensitization failed D- frontier signal g: 3. sensitization: successor of g: => l = D, f = 1 several successors of l: => F1 = {o, p} enter next recursion -> n = 0 D- frontier signal h: 4. sensitization: successor of h => m = D, i=1 several successors of m: => F1 = {q, r} enter next recursion -> n =0 <====== n = 0 Learning Level 2 for unjust. gate G: 1. justification k= 1 => Inconsistent with e = D 2. justification k=D => Inconsistent with e = D <====== For unjust. gate G: 1. justification j = 1 => Inconsistent with b = D 2. justification j= D => Inconsistent with b = D <====== D- frontier signal o: 1. sensitization: successor of o: => t = D, n = 0 D- frontier signal p: 2. sensitization: successor of p: => u = D, n = 0 <====== D- frontier signal q: 1. sensitization: successor of q: => v = D, n = 0 D- frontier signal r: 2. sensitization: successor of r: => w = D, n = 0 <====== W. Kunz and P. Menon, “Multilevel Logic Optimization by Implication Analysis,” Proc. Int. Conj: Computer-Aided Design (ICCAD), 1994.

5 ELEC 7250 04/26/055 Boolean Satisfiability (SAT) SAT widely used for Electronic Design Automation (EDA) Design formulation mapped using Conjunctive Normal Form (CNF) Can employ extensively validated algorithms J. M. Silva and L. G. e Silva, “Solving satisfiability in combinational circuits with backtrack search and recursive learning”, XII Symposium on Integrated Circuits and Systems Design, pp,. 192-195, 2000.

6 ELEC 7250 04/26/056 Recursive learning on CNF formulae Learning Level 0 Assignments: y = 1, u = 1, v = 0 Considering y = 1 From w 7 c = 0 or f = 0 Learning Level 1 Considering c = 0 From w 3 a =0 or b = 0 Considering f = 0 From w 6 d = 0 or e = 0 Learning Level 2 Considering a = 0 From w 1 x = 0 Considering b = 0 From w 2 x = 0 (v = 0) Considering d = 0 From w 4 x = 0 Considering e = 0 From w 5 x = 0 (u = 1) J. M. Silva and L. G. e Silva, “Solving satisfiability in combinational circuits”, IEEE Design and Test of computers, pp. 16-21, 2003.

7 ELEC 7250 04/26/057 Performance Both perform the same for circuits with no backtracks (like c1355, c5315) Recursive learning: No aborted faults Computation is faster Occasionally, recursion depth runs high W. Kunz, D. K. Pradhan, "Recursive Learning: A Precise Implication Procedure and its Application to Test Generation in Digital Circuits", IEEE Trans. on Computer-Aided Design of integrated circuits and systems, vol. 13, no. 9, 1994.

8 ELEC 7250 04/26/058 Summary Can be used in combinational as well as sequential circuits Works for different logic alphabets Identifies indirect implications Limiting factor - recursion depth, r max Not necessary in circuits with easy-to-detect solutions


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