Presentation is loading. Please wait.

Presentation is loading. Please wait.

Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 1 DSP C5000 Chapter 3 Addressing Modes Copyright © 2003 Texas Instruments. All rights.

Similar presentations


Presentation on theme: "Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 1 DSP C5000 Chapter 3 Addressing Modes Copyright © 2003 Texas Instruments. All rights."— Presentation transcript:

1 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 1 DSP C5000 Chapter 3 Addressing Modes Copyright © 2003 Texas Instruments. All rights reserved.

2 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 2 Addressing Modes: What are the Problems? Specify operands per instruction: Specify operands per instruction: A single instruction can access several operands at a time thanks to the many internal data busses, A single instruction can access several operands at a time thanks to the many internal data busses, But how do we specify many addresses using a small number of bits? But how do we specify many addresses using a small number of bits? Repeated processing on an array of data: Repeated processing on an array of data: Many DSP operations are repeated on an array of data stored at contiguous addresses in data memory. Many DSP operations are repeated on an array of data stored at contiguous addresses in data memory. There are cases where it is useful to be able to modify the addresses as part of the instruction (increment or decrement). There are cases where it is useful to be able to modify the addresses as part of the instruction (increment or decrement).

3 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 3 Main Addressing Modes of C5000 Family Immediate addressing Immediate addressing Absolute addressing Absolute addressing Direct addressing Direct addressing Indirect addressing by register Indirect addressing by register Support for circular indirect addressing Support for circular indirect addressing Access to Memory Mapped Registers MMRs Access to Memory Mapped Registers MMRs

4 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 4 Allocating Sections

5 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 5Example RAM x[3] RAM y C5000 CPU System Diagram DROM init[3] EPROM(code) y = x1 + x0 + x2 Algorithm How do we allocate the proper sections? Allocate sections (code, constants, vars) Setup addressing modes Add the values (x1 + x0 + x2) Store the result (y) Procedure

6 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 6 Writing relocatable code The programmer should not have to give the exact addresses: The programmer should not have to give the exact addresses: where to read the code in program memory, where to read the code in program memory, where to read the data in data memory. where to read the data in data memory. The assembler allows to use symbolic addresses. The assembler allows to use symbolic addresses. The assembler and the linker work with COFF files: The assembler and the linker work with COFF files: COFF = Common Object File Format. COFF = Common Object File Format. In COFF files, specialized sections are used for code, variables or constants. In COFF files, specialized sections are used for code, variables or constants. The programmer specifies in a command file for the linker where the different sections should be allocated in the memory of the system. The programmer specifies in a command file for the linker where the different sections should be allocated in the memory of the system.

7 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 7 Definition of Sections Different sections for code, vars, constants. Different sections for code, vars, constants. The sections can be initialized or not. The sections can be initialized or not. An initialized section is filled with code or constant values. An initialized section is filled with code or constant values. An uninitialized section reserves memory space for a variable. An uninitialized section reserves memory space for a variable. The sections can have default names or names given by the programmer. The sections can have default names or names given by the programmer.

8 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 8 Definition and names of Sections The programmer uses special directives to identify the sections. The programmer uses special directives to identify the sections.

9 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 9 Example of sections Initialized named section: Initialization of constants. Definition of address tbl Uninitialized named section: x[3], y[1], Definition of address x and y. Initialized named section: code RAM x[3] RAM y 54x CPU System Diagram DROM tbl[3] EPROM code How are these sections placed into the memory areas shown?

10 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 10 C54x Addressing Modes

11 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 11 Format of Data and Instructions, Internal Busses of the C54x Family In the C54x DSP, the data and program memories are organized in 16-bit words. Data busses have a 16-bit width. In the C54x DSP, the data and program memories are organized in 16-bit words. Data busses have a 16-bit width. Data and instructions are generally of size N=16 bits. Data and instructions are generally of size N=16 bits. Some instructions may take several 16-bit words. Some instructions may take several 16-bit words. Some data operands may be double precision and occupy 2 words. Some data operands may be double precision and occupy 2 words. Internal busses: 2 data read, 1 data write Internal busses: 2 data read, 1 data write

12 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 12 Terms from the Users Guide

13 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 13 Immediate Addressing Mode # Instruction contains the value of the operand. Value is preceded by #. Instruction contains the value of the operand. Value is preceded by #. Example: Example: Add the value 4 to the content of accumulator A. Add the value 4 to the content of accumulator A. Useful for initializations. Useful for initializations. Long (16 bits) or short values: Long (16 bits) or short values: For long values: instruction uses 2 words. For long values: instruction uses 2 words. ADD #4,A

14 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 14 Immediate Addressing Mode # 16 bit value 16 bit value 2 words, 2 cycles 2 words, 2 cycles Initialization of ARi for example Initialization of ARi for example Short value Short value 3, 5, 8, 9 bits constant 3, 5, 8, 9 bits constant 1 word, 1 cycle 1 word, 1 cycle To initialize short length registers or bit fields: To initialize short length registers or bit fields: DP, ASM … DP, ASM … Not always available Not always available Example: STM#1234h,AR2 Load AR2 with the value 1234h. Example: LD#6, DP Load DP with the value 6.

15 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 15 Example: MMR (Memory Mapped Registers) and Immediate Addressing STM (STore to Memory-mapped register) stores an immediate value to the specified MMR or Scratch address. #tbl is the 16-bit address of the first element of the array tbl. MMR = Memory Mapped Registers Scratch memory

16 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 16 Direct Addressing Direct addressing = random access from a specified base address. Direct addressing = random access from a specified base address. The instruction contains an offset relative to the base address. The instruction contains an offset relative to the base address. The base address can be the beginning of a data memory page or the stack pointer. The base address can be the beginning of a data memory page or the stack pointer. The data memory is virtually divided in 512 pages of 128 words (512x128 = 2 16 ). The data memory is virtually divided in 512 pages of 128 words (512x128 = 2 16 ). Data Page DP relative direct address Data Page DP relative direct address CPL bit (ComPiler Mode bit) = 0 in ST1 CPL bit (ComPiler Mode bit) = 0 in ST1 Stack Pointer SP relative direct address Stack Pointer SP relative direct address CPL bit = 1 in ST1 CPL bit = 1 in ST1

17 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 17 Data memory pages

18 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 18 Direct Addressing For DP relative mode: For DP relative mode: The 16 bit address is split into 9 MSB and 7 LSB. The 16 bit address is split into 9 MSB and 7 LSB. The 7 LSB of the operand address are given in the instruction, The 7 LSB of the operand address are given in the instruction, The 9 MSB are in the DP register. The 9 MSB are in the DP register. For SP relative mode For SP relative mode The 7 bits given in the instruction are used as an offset from the SP to obtain the address. The 7 bits given in the instruction are used as an offset from the SP to obtain the address. In both cases, only 7 bits are used in the instruction for the operand address. In both cases, only 7 bits are used in the instruction for the operand address.

19 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 19 Direct Addressing OpcodeI=0dma bit dma9-bit DP Instruction DP relative, CPL = 0 Address SP relative, CPL = 1 16-bit Stack Pointer 7-bit dma + 16-bit Data Memory Address Address 9-bit DP DP register SP Register

20 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 20 Direct Addressing example DP = 2, page 2 Offset in the instruction = 1 Address = 0101 in hexadecimal

21 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 21Example This instruction loads the upper 9 bits of address x into DP (in ST0) CPL = 0 To be sure that x and x+1 are in the same page: use Blocking.

22 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 22 Direct Addressing DP relative When DP is initialized, it allows single- word single-cycle instructions with easy to understand symbols for addresses. When DP is initialized, it allows single- word single-cycle instructions with easy to understand symbols for addresses. Defines 512 pages (selected by the 9 bits of DP) of 128 words (selected by the 7 bits in instruction) in data memory. Defines 512 pages (selected by the 9 bits of DP) of 128 words (selected by the 7 bits in instruction) in data memory. CPL is reset by: CPL is reset by: RSBX CPL ; CPL = 0 on reset RSBX CPL ; CPL = 0 on reset Blocking of data in the same page Blocking of data in the same page In the linker command file: In the linker command file:.bss : > RAM BLOCK = 128.bss : > RAM BLOCK = 128 In the assembler file In the assembler file.bss x, 2, 1 ; specify all variables in one page.bss x, 2, 1 ; specify all variables in one page

23 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 23 Direct Addressing SP relative Used by the C compiler Used by the C compiler Useful for stack based operations Useful for stack based operations Controlled by the CPL bit. Set by: Controlled by the CPL bit. Set by: SSBX CPL SSBX CPL

24 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 24 Absolute Addressing Mode *() Allows us to specify a complete operand address in an instruction. *(Address) Allows us to specify a complete operand address in an instruction. *(Address) The address can be in data, program or IO memory. 16 bits. The address can be in data, program or IO memory. 16 bits. 2 words, 2 cycles. 2 words, 2 cycles. Data Memory AddrData.. x: 01FF 1000 y: Acc A data x:.word 1000h y:.word 0500h.text LD*(x),A ADD*(y),A In the *(), the * specifies the type of MEMORY: Data()/Prog()/ Port() Data()/Prog()/ Port()

25 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 25Example RAM x[3] RAM y 54x CPU System Diagram DROM tbl[3] EPROM code Save accumulator A at address y

26 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 26 Indirect Addressing Mode *ARi Compatible with pointers in C. Compatible with pointers in C. 8 ARi Auxiliary Registers to store the addresses of the operands. They are used as pointers. 8 ARi Auxiliary Registers to store the addresses of the operands. They are used as pointers. 2 ARAU = Auxiliary Registers Arithmetic Units to realize operations on the addresses stored in the ARi. 2 ARAU = Auxiliary Registers Arithmetic Units to realize operations on the addresses stored in the ARi. 1 operand (Smem) or 2 operands (Xmem, Ymem) can be specified by indirect addressing in 1 instruction. 1 operand (Smem) or 2 operands (Xmem, Ymem) can be specified by indirect addressing in 1 instruction. Very efficient for DSP operations. Very efficient for DSP operations.

27 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 27 Indirect addressing mode *ARi AR0 can be used as an index. AR0 can be used as an index. Support for circular addressing Support for circular addressing details in next slides details in next slides Bit Reversed BR addressing for FFT Bit Reversed BR addressing for FFT ARi can be modified during the instruction ARi can be modified during the instruction The possible modifications or operations on ARi depend on the number of operands specified by indirect addressing in the instruction. The possible modifications or operations on ARi depend on the number of operands specified by indirect addressing in the instruction. Pointers (ARi) must be initialized before use. Pointers (ARi) must be initialized before use.

28 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 28 Circular buffer and addressing on C54x

29 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 29 Circular addressing with C54x Circular indirect addressing mode: % Circular indirect addressing mode: % *ARi-%, *ARi+%, *ARi-0%, *ARi+0%, *ARi(lk)% *ARi-%, *ARi+%, *ARi-0%, *ARi+0%, *ARi(lk)% In dual operand mode Xmem, Ymem: In dual operand mode Xmem, Ymem: *ARi+0% only valid mode *ARi+0% only valid mode To perform a decrement, store a negative value in AR0. To perform a decrement, store a negative value in AR0. BK register: BK register: Stores the size N of the circular buffer. Stores the size N of the circular buffer. Must be initialized before use. Must be initialized before use. There may be several circular buffers at different addresses at the same time but with the same length. There may be several circular buffers at different addresses at the same time but with the same length.

30 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 30 Limitations on Start Addresses of Circular Buffers If N is written on nb bits in binary, the start address must have its nb LSB at 0: If N is written on nb bits in binary, the start address must have its nb LSB at 0: Examples: Examples: for N=32, 6 LSB of start address =0 for N=32, 6 LSB of start address =0 for N=30, 5 LSB of start address =0 for N=30, 5 LSB of start address =0 To access a circular buffer: To access a circular buffer: Initialize BK with N (nb bits) Initialize BK with N (nb bits) Choose 1 ARi as a pointer Choose 1 ARi as a pointer The effective start address of the buffer is the value in ARi with its nb LSB at 0. The effective start address of the buffer is the value in ARi with its nb LSB at 0. The end address = start addess +N-1. The end address = start addess +N-1.

31 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 31 Indirect Addressing: ARi Specifications and Options for Modification For a single operand Smem: For a single operand Smem: 16 possible options for Smem, 16 possible options for Smem, 4 bits for the option + 3 bits for the ARi. 4 bits for the option + 3 bits for the ARi. The address is specified by = 7 bits. The address is specified by = 7 bits. For 2 operands Xmem, Ymem: For 2 operands Xmem, Ymem: Only 4 ARi can be used: AR2 to AR5. Only 4 ARi can be used: AR2 to AR5. Only 4 possible options for the operations on the ARi. Only 4 possible options for the operations on the ARi. Each address needs = 4 bits, so 2x4=8 bits are necessary for the 2 addresses. Each address needs = 4 bits, so 2x4=8 bits are necessary for the 2 addresses.

32 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 32 Indirect Addressing Options for ARi modifications, Single operand Smem

33 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 33 Indirect Addressing Options for ARi for Double Operand Xmem and Ymem

34 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 34 Indirect Addressing Mode *ARi There are latencies to consider: There are latencies to consider: no latencySTM, MVDK no latencySTM, MVDK 1 cycleMVDM, MVKD, MVDD 1 cycleMVDM, MVKD, MVDD 2 cyclesSTLM, ST, etc 2 cyclesSTLM, ST, etc ARi are read/modified in access phase, so the debugger will appear to show ARs changing early. ARi are read/modified in access phase, so the debugger will appear to show ARs changing early. CMPT must = 0 (bit5, ST1) CMPT must = 0 (bit5, ST1) is 0 on reset is 0 on reset is forced to 0 with RSBX CMPT is forced to 0 with RSBX CMPT CMPT (Compatibility Mode Bit) = 1 allows C2x/C2xx/C5x styled ARP operation for ARs. But this mode is discouraged. CMPT (Compatibility Mode Bit) = 1 allows C2x/C2xx/C5x styled ARP operation for ARs. But this mode is discouraged.

35 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 35Example Initialization of AR1 and AR2. Copy the values from table in DROM to RAM (via A). Indirect addressing allows sequential access to data. RAM x[3] RAM y 54x CPU System Diagram DROM tbl[3] EPROM code

36 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 36 MMR Memory Mapped Registers Addressing MMRs are in page 0 of data memory. MMRs are in page 0 of data memory. They can be accessed by some specific MMR instructions allowing simple access to page 0. They can be accessed by some specific MMR instructions allowing simple access to page 0. In these cases DP, SP and CPL are ignored In these cases DP, SP and CPL are ignored 0000h 0060h 007Fh MMRs Scratch Tip: use the.mmregs directive to allow MMR names to be interpreted as addresses LDM, STLM MMR Acc STM # MMR PSHM, POPM MMR Stack MVDM, MVMD MMR Dmem MVMM AR, SP AR, SP

37 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 37 MMR Memory Mapped Registers Addr. Name(Hex)Description IMR0000Interrupt Mask Register IFR0001Interrupt Flag Register Reserved ST00006Status 0 Register ST10007Status 1 Register AL0008A accumulator low (A[15:00]) AH0009A accumulator high (A[31:16]) AG000AA accumulator guard (A[39:32]) BL000BB accumulator low (B[15:00]) BH000CB accumulator high (B[31:16]) BG000DB accumulator guard (B[39:32]) T000ETemporary Register TRN000FTransition Register Addr. Name(Hex)Description AR00010Address Register 0 AR10011Address Register 1 AR20012Address Register 2 AR30013Address Register 3 AR40014Address Register 4 AR50015Address Register 5 AR60016Address Register 6 AR70017Address Register 7 SP0018Stack Pointer Register BK0019Circular Size Register BRC001ABlock Repeat Counter RSA001BBlock Repeat Start Address REA001CBlock Repeat End Address PMST001DPMST Register E-01FReserved Note: XPC and Peripheral MMR locations are device dependent

38 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 38 MMR Memory Mapped Registers Addressing When accessing MMRs, latencies need to be considered. When accessing MMRs, latencies need to be considered. STM (STore to Memory-mapped register): STM (STore to Memory-mapped register): Stores an immediate value to the specified MMR or Scratch memory address. Stores an immediate value to the specified MMR or Scratch memory address. Writes the values during the access phase of the pipeline to avoid latencies. Writes the values during the access phase of the pipeline to avoid latencies.

39 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 39 Exercise on Addressing Modes of C54x Given: DP=0 DP=4 DP=6 Address/Data (HEX) CPL= CMPT= ProgramABDP AR0AR1AR2 LD#0,DP STM#2,AR0 STM#200h,AR1 STM#300h,AR2 ADD*AR1+,A ADD*AR1+,B,A LD#6,DP ADD*AR2+,A SUB*AR2+,A SUB#32,A ADD*AR1-0,A,B SUB*AR2-0,B,A STLA,62h Addr Mode

40 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 40 Exercise on Addressing Modes of C54x Given: DP=0 DP=4 DP=6 Address/Data (HEX) CPL= CMPT=

41 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 41 Circular buffer and circular addressing A circular buffer of length N is a block of contiguous memory words addressed by a pointer using a modulo N addressing mode. A circular buffer of length N is a block of contiguous memory words addressed by a pointer using a modulo N addressing mode. The 2 extreme words of the memory block are considered as contiguous. The 2 extreme words of the memory block are considered as contiguous. Characteristics of a circular buffer: Characteristics of a circular buffer: Instead of moving the N data in memory, just modify the pointers. Instead of moving the N data in memory, just modify the pointers. When a new data x(n) arrives, the pointer is incremented and the new data is written in place of the oldest one. When a new data x(n) arrives, the pointer is incremented and the new data is written in place of the oldest one.

42 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 42 Trace of Memory and Pointer in a Circular Buffer of Length 3 Very often used for FIR filters. Very often used for FIR filters.

43 Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 43 CODE COMPOSER STUDIO

44 Code Composer Studio Lapplicazione Code Composer Studio (CCS) fornisce un ambiente integrato con le seguenti caratteristiche: Lapplicazione Code Composer Studio (CCS) fornisce un ambiente integrato con le seguenti caratteristiche: Ambiente integrato di svilupo con un editor, debugger, project manager, profiler, etc. Ambiente integrato di svilupo con un editor, debugger, project manager, profiler, etc. Compilatore C/C++, ottimizzatore assembly e linker (code generation tools). Compilatore C/C++, ottimizzatore assembly e linker (code generation tools). Simulatore. Simulatore. Sistema operativo Real-time (DSP/BIOS). Sistema operativo Real-time (DSP/BIOS). Passaggio Real-Time dei dati da PC a DSK (RTDX). Passaggio Real-Time dei dati da PC a DSK (RTDX). Analisi Real-time visualizzazione dei dati. Analisi Real-time visualizzazione dei dati.

45 Code Composer Studio Il Code Composer Studio comprende: Editor / Debugger Integrati Editor / Debugger Integrati Simulatore * Simulatore * PLUG INS Esterne Edit SIM Compiler Asm Opt Asm DSK EVM SchedeEmbedded Standard Runtime Libraries Strumenti per generaz. Codice Strumenti per generaz. Codice BIOS:Real-time kernel Real-time analysis BIOS:Real-time kernel Real-time analysis Plug-ins Plug-ins RTDX RTDX DSP/BIOSLibrariesDSP/BIOSConfigTool Debug.outLink * Simulator not included with DSK, only with full version of CCS.

46 Esempio di utilizzo CCS Implementiamo: con: a i = {40, 39, …, 1} x i = {1, 2, …, 40} (1)Creiamo una directory di lavoro e copiamo I seguenti files: (a)lab.cmd (b) vectors.asm (c)lab.c (2)Creiamo un nuovo progetto: (a)Avviare CCS. (b)Creare il nuovo progetto come indicato nelle slide successive.

47 Esempio di utilizzo CCS

48 (3)Add files to the project (lab.c, lab.cmd, vector.asm).

49 Esempio di utilizzo CCS (4)Cambiare le opzioni di compilazione e link:

50 Esempio di utilizzo CCS (5)Creare il programma eseguibile (lab.out): (a)Procedure alternative: (i)Cliccare licona Rebuild All. (ii)Selezionare Rebuild All nel menù project. (b)Verificare nella finestra di output il buon esito della compilazione (viene mostrato 0 errors, 0 warnings:

51 Esempio di utilizzo CCS (6)Caricare leseguibile lab.out nella memoria del DSP: (b)Caricare lab.out selezionando File:Load Program come mostrato sotto:

52 Esempio di utilizzo CCS (7)Eseguire e debuggare il codice: (a)Andare allinizio del programma, main() selezionando Debug:Go Main. (b)Esamina variabili: (i) Selezionare la variabile (da esaminare) dal file lab.c, right click e selezionare Add To Watch Window. Se la variabile ad esempio è y, verrà mostarta la seguente finestra.

53 Esempio di utilizzo CCS (7) Eseguire e debuggare il codice: : (c) E possibile eseguire completamente o passo passo il codice utilizzando le varie icone sulla barra o tramite il menù Debug:

54 SVILUPPARE CODICE IN C

55 Sviluppare codice in c Alla luce di quanto visto, sviluppare codice in linguaggio C non presenta particolari difficoltà. E possibile creare codice su PC e poi farlo girare su DSP senza problemi: La libreria standard del C è pienamente supportata (rts.lib). La libreria standard del C è pienamente supportata (rts.lib). E possibile utillizzare le classiche funzioni di I/O su schermo o file, printf(), fprintf(), scanf() etc…e di allocazione dinamica della memoria come la malloc().. E possibile utillizzare le classiche funzioni di I/O su schermo o file, printf(), fprintf(), scanf() etc…e di allocazione dinamica della memoria come la malloc().. Unico accorgimento è sui tipi di dato. Il compilatore per DSP C5x implementa alcuni tipi di dato in maniera differente dai comuni compilatori per PC. Es: long, int etc… Unico accorgimento è sui tipi di dato. Il compilatore per DSP C5x implementa alcuni tipi di dato in maniera differente dai comuni compilatori per PC. Es: long, int etc…

56 Tipi di dato C5402 Tipo Dimensione Rappresentazione char, signed char16 bitsASCII unsigned char16 bitsASCII short16 bits2s complement unsigned short16 bitsbinary int, signed int16 bits2s complement unsigned int16 bitsbinary long, signed long32 bits 2s complement unsigned long32 bits binary enum16 bits 2s complement float32 bits IEEE 32-bit double32 bits IEEE 64-bit long double32 bits IEEE 64-bit pointers16 bits binary !

57 Scrivere Codice in C Quando si compila codice scritto in C, ricordarsi di linkare anche la libreria C, chiamata rts.lib Codice C Libreria rts.lib Codice assembly Compilatore AssemblerLinker CodiceEseguibile.lib.asm.asm.obj.c E possibile trovare la rts.lib in: C:\ti\c6000\cgtools\lib

58 Ingredienti per sviluppare un codice eseguibile su C5402

59 Cosa serve per creare un codice eseguibile su C5402 Per creare un codice.out, in ambiente CCS da caricare sul nostro processore sono necessari alcuni file di supporto: 1.Processo.c : questo è il nostro file creato in C che effettua lelaborazione vera e propria sul segnale. 2.Rts.lib : libreria da linkare assieme al codice. Impelmenta tra le altre cose, tutte le funzioni di uso comune (printf(), etc..) 3.Vector.asm: E la tabella dei vettori da caricare a partire dalla locazione 0x0. Quando viene effettuato il reset, la CPU, tramite questa tabella salta al main() del nostro codice C. 4..cmd: In questo file si specifica come è strutturata la memoria interna ed esterna della CPU. Serve al linker per poter rilocare il codice. Processo.cCompilatoreAssembler Rts.lib Linker Vectros.asm.cmd.out


Download ppt "Trestino Cosmo Università degli studi di Padova Capitolo 2, Slide 1 DSP C5000 Chapter 3 Addressing Modes Copyright © 2003 Texas Instruments. All rights."

Similar presentations


Ads by Google