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DSP C5000 Chapter 3 Addressing Modes Copyright © 2003 Texas Instruments. All rights reserved.

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1 DSP C5000 Chapter 3 Addressing Modes Copyright © 2003 Texas Instruments. All rights reserved.

2 ESIEE, Slide 2Objectives Present the main addressing modes and allocation of sections Present the main addressing modes and allocation of sections Present the main addressing modes of the C54 family Present the main addressing modes of the C54 family Present the main addressing modes of the C55 family Present the main addressing modes of the C55 family Explain how to use these addressing modes Explain how to use these addressing modes Do exercises to practice using the different addressing modes Do exercises to practice using the different addressing modes

3 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 3Outline Generalities on addressing modes Generalities on addressing modes C54x C54x C55x C55x

4 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 4 Addressing Modes: What are the Problems? Specify operands per instruction: Specify operands per instruction: A single instruction can access several operands at a time thanks to the many internal data busses, A single instruction can access several operands at a time thanks to the many internal data busses, But how do we specify many addresses using a small number of bits? But how do we specify many addresses using a small number of bits? Repeated processing on an array of data: Repeated processing on an array of data: Many DSP operations are repeated on an array of data stored at contiguous addresses in data memory. Many DSP operations are repeated on an array of data stored at contiguous addresses in data memory. There are cases where it is useful to be able to modify the addresses as part of the instruction (increment or decrement). There are cases where it is useful to be able to modify the addresses as part of the instruction (increment or decrement).

5 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 5 Main Addressing Modes of C5000 Family Immediate addressing Immediate addressing Absolute addressing Absolute addressing Direct addressing Direct addressing Indirect addressing by register Indirect addressing by register Support for circular indirect addressing Support for circular indirect addressing Definition Definition Definition Access to Memory Mapped Registers MMRs Access to Memory Mapped Registers MMRs

6 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 6 Allocating Sections

7 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 7Example RAM x[3] RAM y C5000 CPU System Diagram DROM init[3] EPROM(code) y = x1 + x0 + x2 Algorithm How do we allocate the proper sections? Allocate sections (code, constants, vars) Setup addressing modes Add the values (x1 + x0 + x2) Store the result (y) Procedure

8 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 8 Writing relocatable code The programmer should not have to give the exact addresses: The programmer should not have to give the exact addresses: where to read the code in program memory, where to read the code in program memory, where to read the data in data memory. where to read the data in data memory. The assembler allows to use symbolic addresses. The assembler allows to use symbolic addresses. The assembler and the linker work with COFF files: The assembler and the linker work with COFF files: COFF = Common Object File Format. COFF = Common Object File Format. In COFF files, specialized sections are used for code, variables or constants. In COFF files, specialized sections are used for code, variables or constants. The programmer specifies in a command file for the linker where the different sections should be allocated in the memory of the system. The programmer specifies in a command file for the linker where the different sections should be allocated in the memory of the system.

9 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 9 Definition of Sections Different sections for code, vars, constants. Different sections for code, vars, constants. The sections can be initialized or not. The sections can be initialized or not. An initialized section is filled with code or constant values. An initialized section is filled with code or constant values. An uninitialized section reserves memory space for a variable. An uninitialized section reserves memory space for a variable. The sections can have default names or names given by the programmer. The sections can have default names or names given by the programmer.

10 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 10 Definition and names of Sections The programmer uses special directives to identify the sections. The programmer uses special directives to identify the sections.

11 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 11 Example of sections Initialized named section: Initialization of constants. Definition of address tbl Uninitialized named section: x[3], y[1], Definition of address x and y. Initialized named section: code RAM x[3] RAM y 54x CPU System Diagram DROM tbl[3] EPROM code How are these sections placed into the memory areas shown?

12 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 12 C54x Addressing Modes

13 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 13 Format of Data and Instructions, Internal Busses of the C54x Family In the C54x DSP, the data and program memories are organized in 16-bit words. Data busses have a 16-bit width. In the C54x DSP, the data and program memories are organized in 16-bit words. Data busses have a 16-bit width. Data and instructions are generally of size N=16 bits. Data and instructions are generally of size N=16 bits. Some instructions may take several 16-bit words. Some instructions may take several 16-bit words. Some data operands may be double precision and occupy 2 words. Some data operands may be double precision and occupy 2 words. Internal busses: 2 data read, 1 data write Internal busses: 2 data read, 1 data write

14 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 14 Terms from the Users Guide

15 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 15 Immediate Addressing Mode # Instruction contains the value of the operand. Value is preceded by #. Instruction contains the value of the operand. Value is preceded by #. Example: Example: Add the value 4 to the content of accumulator A. Add the value 4 to the content of accumulator A. Useful for initializations. Useful for initializations. Long (16 bits) or short values: Long (16 bits) or short values: For long values: instruction uses 2 words. For long values: instruction uses 2 words. ADD #4,A

16 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 16 Immediate Addressing Mode # 16 bit value 16 bit value 2 words, 2 cycles 2 words, 2 cycles Initialization of ARi for example Initialization of ARi for example Short value Short value 3, 5, 8, 9 bits constant 3, 5, 8, 9 bits constant 1 word, 1 cycle 1 word, 1 cycle To initialize short length registers or bit fields: To initialize short length registers or bit fields: DP, ASM … DP, ASM … Not always available Not always available Example: STM#1234h,AR2 Load AR2 with the value 1234h. Example: LD#6, DP Load DP with the value 6.

17 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 17 Example: MMR (Memory Mapped Registers) and Immediate Addressing STM (STore to Memory-mapped register) stores an immediate value to the specified MMR or Scratch address. #tbl is the 16-bit address of the first element of the array tbl. MMR = Memory Mapped Registers Scratch memory

18 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 18 Direct Addressing Direct addressing = random access from a specified base address. Direct addressing = random access from a specified base address. The instruction contains an offset relative to the base address. The instruction contains an offset relative to the base address. The base address can be the beginning of a data memory page or the stack pointer. The base address can be the beginning of a data memory page or the stack pointer. The data memory is virtually divided in 512 pages of 128 words (512x128 = 2 16 ). The data memory is virtually divided in 512 pages of 128 words (512x128 = 2 16 ). Data Page DP relative direct address Data Page DP relative direct address CPL bit (ComPiler Mode bit) = 0 in ST1 CPL bit (ComPiler Mode bit) = 0 in ST1 Stack Pointer SP relative direct address Stack Pointer SP relative direct address CPL bit = 1 in ST1 CPL bit = 1 in ST1

19 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 19 Data memory pages

20 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 20 Direct Addressing For DP relative mode: For DP relative mode: The 16 bit address is split into 9 MSB and 7 LSB. The 16 bit address is split into 9 MSB and 7 LSB. The 7 LSB of the operand address are given in the instruction, The 7 LSB of the operand address are given in the instruction, The 9 MSB are in the DP register. The 9 MSB are in the DP register. For SP relative mode For SP relative mode The 7 bits given in the instruction are used as an offset from the SP to obtain the address. The 7 bits given in the instruction are used as an offset from the SP to obtain the address. In both cases, only 7 bits are used in the instruction for the operand address. In both cases, only 7 bits are used in the instruction for the operand address.

21 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 21 Direct Addressing OpcodeI=0dma bit dma9-bit DP Instruction DP relative, CPL = 0 Address SP relative, CPL = 1 16-bit Stack Pointer 7-bit dma + 16-bit Data Memory Address Address 9-bit DP DP register SP Register

22 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 22 Direct Addressing example DP = 2, page 2 Offset in the instruction = 1 Address = 0101 in hexadecimal

23 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 23Example This instruction loads the upper 9 bits of address x into DP (in ST0) CPL = 0 To be sure that x and x+1 are in the same page: use Blocking.

24 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 24 Direct Addressing DP relative When DP is initialized, it allows single- word single-cycle instructions with easy to understand symbols for addresses. When DP is initialized, it allows single- word single-cycle instructions with easy to understand symbols for addresses. Defines 512 pages (selected by the 9 bits of DP) of 128 words (selected by the 7 bits in instruction) in data memory. Defines 512 pages (selected by the 9 bits of DP) of 128 words (selected by the 7 bits in instruction) in data memory. CPL is reset by: CPL is reset by: RSBX CPL ; CPL = 0 on reset RSBX CPL ; CPL = 0 on reset Blocking of data in the same page Blocking of data in the same page In the linker command file: In the linker command file:.bss : > RAM BLOCK = 128.bss : > RAM BLOCK = 128 In the assembler file In the assembler file.bss x, 2, 1 ; specify all variables in one page.bss x, 2, 1 ; specify all variables in one page

25 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 25 Direct Addressing SP relative Used by the C compiler Used by the C compiler Useful for stack based operations Useful for stack based operations Controlled by the CPL bit. Set by: Controlled by the CPL bit. Set by: SSBX CPL SSBX CPL

26 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 26 Indirect Addressing Mode *ARi Compatible with pointers in C. Compatible with pointers in C. 8 ARi Auxiliary Registers to store the addresses of the operands. They are used as pointers. 8 ARi Auxiliary Registers to store the addresses of the operands. They are used as pointers. 2 ARAU = Auxiliary Registers Arithmetic Units to realize operations on the addresses stored in the ARi. 2 ARAU = Auxiliary Registers Arithmetic Units to realize operations on the addresses stored in the ARi. 1 operand (Smem) or 2 operands (Xmem, Ymem) can be specified by indirect addressing in 1 instruction. 1 operand (Smem) or 2 operands (Xmem, Ymem) can be specified by indirect addressing in 1 instruction. Very efficient for DSP operations. Very efficient for DSP operations.

27 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 27 Indirect addressing mode *ARi AR0 can be used as an index. AR0 can be used as an index. Support for circular addressing Support for circular addressing details in next slides details in next slides Bit Reversed BR addressing for FFT Bit Reversed BR addressing for FFT ARi can be modified during the instruction ARi can be modified during the instruction The possible modifications or operations on ARi depend on the number of operands specified by indirect addressing in the instruction. The possible modifications or operations on ARi depend on the number of operands specified by indirect addressing in the instruction. Pointers (ARi) must be initialized before use. Pointers (ARi) must be initialized before use.

28 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 28 Circular buffer and addressing on C54x

29 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 29 Circular addressing with C54x Circular indirect addressing mode: % Circular indirect addressing mode: % *ARi-%, *ARi+%, *ARi-0%, *ARi+0%, *ARi(lk)% *ARi-%, *ARi+%, *ARi-0%, *ARi+0%, *ARi(lk)% In dual operand mode Xmem, Ymem: In dual operand mode Xmem, Ymem: *ARi+0% only valid mode *ARi+0% only valid mode To perform a decrement, store a negative value in AR0. To perform a decrement, store a negative value in AR0. BK register: BK register: Stores the size N of the circular buffer. Stores the size N of the circular buffer. Must be initialized before use. Must be initialized before use. There may be several circular buffers at different addresses at the same time but with the same length. There may be several circular buffers at different addresses at the same time but with the same length.

30 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 30 Limitations on Start Addresses of Circular Buffers If N is written on nb bits in binary, the start address must have its nb LSB at 0: If N is written on nb bits in binary, the start address must have its nb LSB at 0: Examples: Examples: for N=32, 6 LSB of start address =0 for N=32, 6 LSB of start address =0 for N=30, 5 LSB of start address =0 for N=30, 5 LSB of start address =0 To access a circular buffer: To access a circular buffer: Initialize BK with N (nb bits) Initialize BK with N (nb bits) Choose 1 ARi as a pointer Choose 1 ARi as a pointer The effective start address of the buffer is the value in ARi with its nb LSB at 0. The effective start address of the buffer is the value in ARi with its nb LSB at 0. The end address = start addess +N-1. The end address = start addess +N-1.

31 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 31 Indirect Addressing: ARi Specifications and Options for Modification For a single operand Smem: For a single operand Smem: 16 possible options for Smem, 16 possible options for Smem, 4 bits for the option + 3 bits for the ARi. 4 bits for the option + 3 bits for the ARi. The address is specified by = 7 bits. The address is specified by = 7 bits. For 2 operands Xmem, Ymem: For 2 operands Xmem, Ymem: Only 4 ARi can be used: AR2 to AR5. Only 4 ARi can be used: AR2 to AR5. Only 4 possible options for the operations on the ARi. Only 4 possible options for the operations on the ARi. Each address needs = 4 bits, so 2x4=8 bits are necessary for the 2 addresses. Each address needs = 4 bits, so 2x4=8 bits are necessary for the 2 addresses.

32 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 32 Indirect Addressing Options for ARi modifications, Single operand Smem

33 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 33 Indirect Addressing Options for ARi for Double Operand Xmem and Ymem

34 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 34 Indirect Addressing Mode *ARi There are latencies to consider: There are latencies to consider: no latencySTM, MVDK no latencySTM, MVDK 1 cycleMVDM, MVKD, MVDD 1 cycleMVDM, MVKD, MVDD 2 cyclesSTLM, ST, etc 2 cyclesSTLM, ST, etc ARi are read/modified in access phase, so the debugger will appear to show ARs changing early. ARi are read/modified in access phase, so the debugger will appear to show ARs changing early. CMPT must = 0 (bit5, ST1) CMPT must = 0 (bit5, ST1) is 0 on reset is 0 on reset is forced to 0 with RSBX CMPT is forced to 0 with RSBX CMPT CMPT (Compatibility Mode Bit) = 1 allows C2x/C2xx/C5x styled ARP operation for ARs. But this mode is discouraged. CMPT (Compatibility Mode Bit) = 1 allows C2x/C2xx/C5x styled ARP operation for ARs. But this mode is discouraged.

35 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 35Example Initialization of AR1 and AR2. Copy the values from table in DROM to RAM (via A). Indirect addressing allows sequential access to data. RAM x[3] RAM y 54x CPU System Diagram DROM tbl[3] EPROM code

36 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 36 Absolute Addressing Mode *() Allows us to specify a complete operand address in an instruction. *(Address) Allows us to specify a complete operand address in an instruction. *(Address) The address can be in data, program or IO memory. 16 bits. The address can be in data, program or IO memory. 16 bits. 2 words, 2 cycles. 2 words, 2 cycles. Data Memory AddrData.. x: 01FF 1000 y: Acc A data x:.word 1000h y:.word 0500h.text LD*(x),A ADD*(y),A

37 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 37Example RAM x[3] RAM y 54x CPU System Diagram DROM tbl[3] EPROM code Save accumulator A at address y

38 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 38 MMR Memory Mapped Registers Addressing MMRs are in page 0 of data memory. MMRs are in page 0 of data memory. They can be accessed by some specific MMR instructions allowing simple access to page 0. They can be accessed by some specific MMR instructions allowing simple access to page 0. In these cases DP, SP and CPL are ignored In these cases DP, SP and CPL are ignored 0000h 0060h 007Fh MMRs Scratch Tip: use the.mmregs directive to allow MMR names to be interpreted as addresses LDM, STLM MMR Acc STM # MMR PSHM, POPM MMR Stack MVDM, MVMD MMR Dmem MVMM AR, SP AR, SP

39 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 39 MMR Memory Mapped Registers Addr. Name(Hex)Description IMR0000Interrupt Mask Register IFR0001Interrupt Flag Register Reserved ST00006Status 0 Register ST10007Status 1 Register AL0008A accumulator low (A[15:00]) AH0009A accumulator high (A[31:16]) AG000AA accumulator guard (A[39:32]) BL000BB accumulator low (B[15:00]) BH000CB accumulator high (B[31:16]) BG000DB accumulator guard (B[39:32]) T000ETemporary Register TRN000FTransition Register Addr. Name(Hex)Description AR00010Address Register 0 AR10011Address Register 1 AR20012Address Register 2 AR30013Address Register 3 AR40014Address Register 4 AR50015Address Register 5 AR60016Address Register 6 AR70017Address Register 7 SP0018Stack Pointer Register BK0019Circular Size Register BRC001ABlock Repeat Counter RSA001BBlock Repeat Start Address REA001CBlock Repeat End Address PMST001DPMST Register E-01FReserved Note: XPC and Peripheral MMR locations are device dependent

40 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 40 MMR Memory Mapped Registers Addressing When accessing MMRs, latencies need to be considered. When accessing MMRs, latencies need to be considered. STM (STore to Memory-mapped register): STM (STore to Memory-mapped register): Stores an immediate value to the specified MMR or Scratch memory address. Stores an immediate value to the specified MMR or Scratch memory address. Writes the values during the access phase of the pipeline to avoid latencies. Writes the values during the access phase of the pipeline to avoid latencies.

41 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 41 Exercise on Addressing Modes of C54x Given: DP=0 DP=4 DP=6 Address/Data (HEX) CPL= CMPT= ProgramABDP AR0AR1AR2 LD#0,DP STM#2,AR0 STM#200h,AR1 STM#300h,AR2 ADD*AR1+,A ADD*AR1+,B,A LD#6,DP ADD*AR2+,A SUB*AR2+,A SUB#32,A ADD*AR1-0,A,B SUB*AR2-0,B,A STLA,62h Addr Mode

42 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 42 Exercise on Addressing Modes of C54x Given: DP=0 DP=4 DP=6 Address/Data (HEX) CPL= CMPT=

43 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 43 C55x Addressing Modes

44 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 44 Format of Data and Instructions, Internal Busses for the C55x Family Unified program-data memory map: byte-aligned for program and word- aligned for data. Unified program-data memory map: byte-aligned for program and word- aligned for data. Has a variable length instruction set ( bits). Has a variable length instruction set ( bits). Program address bus: 24 bits, 16 Mbytes Program address bus: 24 bits, 16 Mbytes 4 instructions bytes are fetched at a time 4 instructions bytes are fetched at a time 6 bytes are decoded at a time 6 bytes are decoded at a time Internal data busses: 3 data read, 2 data write Internal data busses: 3 data read, 2 data write Data addresses: 8 Mwords of 16 bits segmented into 64K pages, 23-bit address. A 24-bit address is automatically generated by the hardware by adding a LSB = 0. Data addresses: 8 Mwords of 16 bits segmented into 64K pages, 23-bit address. A 24-bit address is automatically generated by the hardware by adding a LSB = 0.

45 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 45 C55x Addressing Modes Direct Direct Indirect Indirect Absolute Absolute MMR MMR Loading constants in registers (e.g. immediate) Loading constants in registers (e.g. immediate) y = x0 + x1 + x2 Algorithm RAM x[3] RAMy IP DA 55xx CPU System Diagram ROM tbl[3] y = x0 + x1 + x2 This algorithm will again be used as an example for the different addressing modes.

46 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 46 Loading Constants in Registers # Used for initialization of registers. Used for initialization of registers. Used to be called immediate addressing Used to be called immediate addressing Addressing registers: Addressing registers: 16-bits long: ARi, DP, CDP (Coefficient Data Pointer) 16-bits long: ARi, DP, CDP (Coefficient Data Pointer) 23-bits long: XARi, XDP, XCDP 23-bits long: XARi, XDP, XCDP The 7 MSB of Xreg specify the 64K page. The 7 MSB of Xreg specify the 64K page. The ARAU auxiliary Register Arithmetic Unit is 16 bits wide: update of ARi and CDP are done modulo 64K. The ARAU auxiliary Register Arithmetic Unit is 16 bits wide: update of ARi and CDP are done modulo 64K. Initialization example: Initialization example: AMOV #adr,XAR3

47 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 47Example x.usect vars,4 y.usect vars,1.sect init.sect init tbl.int 1,2,3,4.sect code.sect code indir: AMOV #x,XAR0 AMOV #tbl,XAR6 AMOV #tbl,XAR6 RAM x[3] RAMy IP DA 55xx CPU ROM tbl[3] y = x0 + x1 + x2 = 23-bit address 16-bit ARn 23-bit XARn X

48 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 48 Direct Addressing Gives the instruction a positive 7bit offset from DP (non-aligned). Gives the instruction a positive 7bit offset from DP (non-aligned). In the case where the bit CPL=0 in ST1. In the case where the bit CPL=0 in ST1. Calculation in the ARAU modulo 64K Calculation in the ARAU modulo 64K = + 23-bit address 16-bit DP 23-bit XDP X

49 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 49Example x.usect vars,4 y.usect vars,1.sect init.sect init tbl.int 1,2,3,4.sect code.sect code How is XDP initialized? RAM x[3] RAMy IP DA 55xx CPU ROM tbl[3] y = x0 + x1 + x2

50 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 50Example Constant value contained in instruction opcode Constant value contained in instruction opcode (-x) used in instruction to tell the assembler HOW to create the 7-bit offset from non-aligned XDP (-x) used in instruction to tell the assembler HOW to create the 7-bit offset from non-aligned XDP A in AMOV means in AD-phase. The MDP has to be reloaded every time we cross a 64K page.

51 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 51 Directive.dp for Direct Addressing Instead of using (-x) to help the assembler calculate the proper 7-bit offset, Instead of using (-x) to help the assembler calculate the proper 7-bit offset, We can use the directive.dp to set the base address for the assembler calculation of the 7-bit offset. We can use the directive.dp to set the base address for the assembler calculation of the 7-bit offset..dp base_address.dp base_address in the instruction is interpreted as a 23-bit address. The.dp provides a compile-time base address. The assembler determines the 7-bit offset by:

52 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 52 Indirect Addressing Mode *ARi Similar to the case of the C54x, but: Similar to the case of the C54x, but: 23-bit addresses, 23-bit addresses, Extended registers XARi on 23 bits specify the complete address, Extended registers XARi on 23 bits specify the complete address, ARAU calculates on 16 bits (modulo 64K), ARAU calculates on 16 bits (modulo 64K), 8 ARi 16-bit pointers used in the instructions. 8 ARi 16-bit pointers used in the instructions.

53 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 53 Indirect Addressing Options for Pointer ARi Modifications Assumes ST2_55 ARMS =0 and ST1_55 C54CM =0. Assumes ST2_55 ARMS =0 and ST1_55 C54CM =0. The reset condition is C54CM=1. The reset condition is C54CM=1.

54 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 54 Address Register Mode Select Bit ARMS ARMS bit = bit 15 of ST2_55 ARMS bit = bit 15 of ST2_55 ARMS=0 at reset DSP mode ARMS=0 at reset DSP mode For ARMS=1, CONTROL mode For ARMS=1, CONTROL mode T1 cannot be used as offset T1 cannot be used as offset No bit reversed addressing No bit reversed addressing New mode: New mode: *ARi(short(#k3)) or *SP(short(#k3)) *ARi(short(#k3)) or *SP(short(#k3)) Useful for the C compiler Useful for the C compiler The C compiler sets ARMS = 1. The C compiler sets ARMS = 1.

55 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 55 Modifying TAs Registers TAx registers = T0-3, AR0-7. TAx registers = T0-3, AR0-7. Special instructions: Special instructions: AADD, ASUB, AMOV AADD, ASUB, AMOV Can be used to modify TAs registers during the address (AD) phase of the pipeline, while instructions without A operates during the execution (X) phase. Can be used to modify TAs registers during the address (AD) phase of the pipeline, while instructions without A operates during the execution (X) phase. They only work on the TAx registers. They only work on the TAx registers. Examples:

56 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 56Example + + RAMx[4] RAMy IP DA 55xx CPU ROMtbl[4] y = x0 + x1 + x1

57 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 57 Circular Buffer Addressing Mode

58 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 58 Circular Buffer Addressing Mode The even XARn (i.e. 0,2,4,6) determines the 64K Page

59 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 59 Selecting Circular or Linear Addressing Mode Use the LSB of Status word ST2_55 Use the LSB of Status word ST2_55 Set or reset status bits: Set or reset status bits:

60 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 60 Circular Buffer Exercise Use AR4 as a circular pointer to x{5}: Results are cumulative

61 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 61 Comparison of C54x and C55x circular addressing modes 3 BK registers in C55X instead of 1 in C54x: allows for several simultaneous circular buffers with different size. 3 BK registers in C55X instead of 1 in C54x: allows for several simultaneous circular buffers with different size. In C54x, circular addressing mode is specified in indirect addressing type % in the instructions. In C54x, circular addressing mode is specified in indirect addressing type % in the instructions. In C55x, the mode in set in status register ST2_55 for each register (linear or circular). No memory alignment constraint. In C55x, the mode in set in status register ST2_55 for each register (linear or circular). No memory alignment constraint.

62 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 62 Absolute Addressing *(#) *(#) = 23 bit address *(#) = 23 bit address Fast: no initialization, Fast: no initialization, But long instruction because it contains the 23 bit address. But long instruction because it contains the 23 bit address. If the address is in the 64K work page, it is possible to specify a 16-bit only address: If the address is in the 64K work page, it is possible to specify a 16-bit only address: abs16*(#label) abs16*(#label)

63 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 63ExampleRAMx[4] RAMy IP DA 55xx CPU ROMtbl[4] y = x0 + x1 + x2

64 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 64 MMR Addressing Using mmap() MMRs are located between 0 and 5F. MMRs are located between 0 and 5F. Scratch memory is located between 60 and 7F. Scratch memory is located between 60 and 7F. mmap() forces bits 22:7 to zero. mmap() forces bits 22:7 to zero. Useful to access MMR and scratch memory without initialization of addressing registers. Useful to access MMR and scratch memory without initialization of addressing registers. Useful only for direct addressing. Useful only for direct addressing.

65 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 65 Access Peripheral Registers The I/O space is internal. The I/O space is internal. The PDP (Peripheral Data Pointer) register is used to access ports using direct addressing. The PDP (Peripheral Data Pointer) register is used to access ports using direct addressing. It is a 9bit register. Its value is concatenated with the 7 bits in the instruction to obtain a full 16-bit peripheral address. It is a 9bit register. Its value is concatenated with the 7 bits in the instruction to obtain a full 16-bit peripheral address. The port() modifier selects the peripheral map The port() modifier selects the peripheral map

66 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 66 Access Peripheral Registers 0000h FFFFh I/O - Peripheral Memory Map DMA McBSP EHPI EMIF Timers Power Dwn Instr Cache GPIO abs: MOV port(#addr),T1 dir: MOV #addr,PDP MOV MOV indir: AMOV #addr,AR4 MOV port(*AR4),T1 MOV port(*AR4),T1

67 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 67 Directives for Addressing Modes 3 Mode bits affect addressing: 3 Mode bits affect addressing: ARMS: Address Register Mode Select ARMS: Address Register Mode Select C54CM: C54 Compatibility Mode C54CM: C54 Compatibility Mode C54CM=1 on reset, native C55x coding requires C54CM=0. C54CM=1 on reset, native C55x coding requires C54CM=0. CPL: ComPiLer Mode CPL: ComPiLer Mode 3 directives help the assembler to check the syntax and responds with ERROR in case of inconsistency: 3 directives help the assembler to check the syntax and responds with ERROR in case of inconsistency:.arms_on or.arms_off.arms_on or.arms_off.c54cm_on or.c54cm_off.c54cm_on or.c54cm_off.cpl_onor.cpl_off.cpl_onor.cpl_off

68 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 68 Modifying Status Bits BCLR ARMS;clear ARMS BSET CPL;set CPL BCLR C54CM;clear C54CM BSET/BCLR bit_name

69 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 69 Addressing Exercise 02_0105h 21h x = 02_0106h 02_0107h 02_0108h 02_0206h XDP XDP The initial state of each instruction is shown here... The initial state of each instruction is shown here... Below, write down the state after each instr Below, write down the state after each instr 30h 40h 50h 60h XAR1 T0 2 02_0106h 02_0106h.dp x

70 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 70 Addressing Exercise – Solution 02_0105h 21h x = 02_0106h 02_0107h 02_0108h 02_0206h XDP XDP The initial state of each instruction is shown here... The initial state of each instruction is shown here... Below, write down the state after each instr Below, write down the state after each instr 30h 40h 50h 60h XAR1 T0 2 02_0106h 02_0106h.dp x

71 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 71

72 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 72 Circular buffer and circular addressing A circular buffer of length N is a block of contiguous memory words addressed by a pointer using a modulo N addressing mode. A circular buffer of length N is a block of contiguous memory words addressed by a pointer using a modulo N addressing mode. The 2 extreme words of the memory block are considered as contiguous. The 2 extreme words of the memory block are considered as contiguous. Characteristics of a circular buffer: Characteristics of a circular buffer: Instead of moving the N data in memory, just modify the pointers. Instead of moving the N data in memory, just modify the pointers. When a new data x(n) arrives, the pointer is incremented and the new data is written in place of the oldest one. When a new data x(n) arrives, the pointer is incremented and the new data is written in place of the oldest one.

73 Copyright © 2003 Texas Instruments. All rights reserved. ESIEE, Slide 73 Trace of Memory and Pointer in a Circular Buffer of Length 3 Very often used for FIR filters. Very often used for FIR filters.


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