1. Reouven Elbaz – February 10 th, 2009 reouven@uwaterloo.ca Office room: DC3576 ECE223

2. Outline Multiplexers Decoders 3-state Gates Read Only Memories (ROM)

3. Multiplexers A 2 n -to-1 multiplexer selects one of its 2 n input values and outputs it – data selector. How?  Using control signals that encode the position of the targeted input… How many control signals?  For 2 n inputs, n control signals MUX 8-to-1 I0I0 I1I1 I2I2 I3I3 I4I4 I5I5 I6I6 I7I7 Output ab c I3I3 I6I6 I7I7

4. 2-to-1 Multiplexer Output = aI 0 + a’I 1 MUX I0I0 I1I1 Output a 2-to-1 aOutput 0 1 I1I1 I0I0

5. 4-to-1 Multiplexer Output = a’b’I 0 + a’bI 1 + ab’I 2 + abI 3 MUX 4-to-1 I0I0 I1I1 I2I2 I3I3 Output ab ab 00I0I0 01I1I1 10I2I2 11I3I3 a’b’I 0 a’bI 1 ab’I 2 abI 3 a'b'

6. General Case: 2 n -to-1 multiplexer I0I0 I1I1 I2I2 I Output 2n2n MUX 2 n -to-1 S0S0 S1S1 SnSn Minterm k of the n control signals Input designated by the minterm k

7. 4-to-1 Multiplexer with Enable eabOutput 100I0I0 101I1I1 110I2I2 111I3I3 MUX 4-to-1 I0I0 I1I1 I2I2 I3I3 Output ab e 0XX0

8. How to construct a 8-to-1 Mux from 4-to-1 Muxes ? MUX 4-to-1 I0I0 I1I1 I2I2 I3I3 O1O1 a b MUX 4-to-1 I4I4 I5I5 I6I6 I7I7 O2O2 e eabO1O1 O2O2 Y 100I0I0 0I0I0 101I1I1 0I1I1 110I2I2 0I2I2 111I3I3 0I3I3 0000I4I4 I4I4 0010I5I5 I5I5 0100I6I6 I6I6 0110I7I7 I7I7 Or Y I4I4 I5I5 I6I6 I7I7 I0I0 I1I1 I2I2 I3I3 ab ab What we want What we have Done!

9. VHDL Example entity Mux4-to-1 is port( I0, I1, I2, I3: in std_logic; CTRL: in std_logic_vector(1 downto 0); Output: out std_logic ); end Mux4-to-1; architecture behav of Mux4-to-1 is begin case CTRL is when "00" => Output <= I0; when "01" => Output <= I1; when "10" => Output <= I2; when "11" => Output <= I3; when others => Output <= I1; end case; end; MUX 4-to-1 I0I0 I1I1 I2I2 I3I3 Output CTRL 2

10. Decoders An n-to-m (m ≤2 n ) decoder converts binary information from n input lines (n-bit coded information) to a maximum of 2 n unique output lines. How?  It generates all the minterms of the n input variables (to have exactly one of the outputs at 1 for each combination of inputs) Example: n=3 and m=8 3-to-8 Decoder I0I0 I1I1 I2I2 O0O0 O1O1 O2O2 O3O3 O4O4 O5O5 O6O6 O7O7

11. Example: 3-to-8 Decoder abcO0O0 O1O1 O2O2 O3O3 O4O4 O5O5 O6O6 O7O7 00010000000 00101000000 01000100000 01100010000 10000001000 10100000100 11000000010 11100000001 3-to-8 Decoder a b c O0O0 O1O1 O2O2 O3O3 O4O4 O5O5 O6O6 O7O7 c b a O 0 = a’b’c’ O 1 = a’b’c O 2 = a’bc’ O 3 = a’bc O 4 = ab’c’ O 5 = ab’c O 6 = abc’ O 7 = abc c’ b’ a’

12. From Decoder to Multiplexer abO0O0 O1O1 O2O2 O3O3 001000 010100 100010 110001 2-to-4 Decoder a b O0O0 O1O1 O2O2 O3O3 b a O 0 = a’b’ O 1 = a’b O 2 = ab’ O 3 = ab b’ a’ abOutput 00I0I0 01I1I1 10I2I2 11I3I3 MUX 4-to-1 I0I0 I1I1 I2I2 I3I3 Output ab b a b’ a’ Output = a’b’I 0 + a’bI 1 + ab’I 2 + abI 3 Or Output I0I0 I1I1 I2I2 I3I3

13. Decoder with Enable Input eabO0O0 O1O1 O2O2 O3O3 0001000 0010100 0100010 0110001 1XX0000 2-to-4 Decoder a b e O0O0 O1O1 O2O2 O3O3 b a O 0 = a’b’e’ O 1 = a’be’ O 2 = ab’e’ O 3 = abe’ b’ a’ e

14. How to construct a 3-to-8 Decoder from 2-to-4 Decoders ? eabO0O0 O1O1 O2O2 O3O3 O4O4 O5O5 O6O6 O7O7 10010000000 10101000000 11000100000 11100010000 00000001000 00100000100 01000000010 01100000001 2-to-4 Decoder a b e O0O0 O1O1 O2O2 O3O3 O4O4 O5O5 O6O6 O7O7

15. VHDL Example entity DECODER2-to-4 is port( I:in std_logic_vector(1 downto 0); O:out std_logic_vector(3 downto 0)); end DECODER2-to-4; architecture behav of DECODER2-to-4 is begin case I is when "00" => O <= "0001"; when "01" => O <= "0010"; when "10" => O <= "0100"; when "11" => O <= "1000"; when others => O <= “0000"; end case; end; 2-to-4 Decoder a b O0O0 O1O1 O2O2 O3O3 I (“ab”) O (“O 1 O 2 O 3 O 4 ”) 2 4

16. 3-state Gates Component exhibiting three states:  Logic ‘1’ and logic ‘0’ states as in conventional gates  High impedance ‘Z’ state. What is high impedance?  (1) The gate behaves like an open circuit – Output disconnected  (2) The circuit has no logic significance  (3) The circuit connected to a 3-state gate in high impedance is not affected by the inputs to the gate. 3-state buffer: s a y = a if s = 1 Z if s = 0

17. a b c d y MUX 4-to-1 Multiplexers constructed from 3-state buffers 1 ay 2 b s MUX a b y s 2-to-1 sy 0a 1b 2-to-1 Mux4-to-1 Mux s0s0 s1s1 y 00a 01b 10c 11d s0s0 s1s1 a y b c d s0s0 s1s1 s2s2 s3s3 2-to-4 Decoder s0s0 s1s1

18. VHDL Example entity 3-state_buffer is port(a:in std_logic_vector(7 downto 0); s: in std_logic; y:out std_logic_vector(7 downto 0)); end 3-state_buffer; architecture behav of 3-state_buffer is begin if s = '1' then y <= a; else y <= "ZZZZZZZZ"; end if; end; s a y = a if s = 1 Z if s = 0 8 8

19. Read Only Memory (ROM) A ROM is a memory where data are permanently stored… A memory that retains data across power cycles. Different types of ROM:  Mask programmable (data defined during the manufacture process)  field-Programmable ROM (PROM): initialization done by user using fusible  Erasable Programmable ROM (EPROM): charge storage is used to program – UV light to erase  EEPROM: use electrical pulses instead of UV light 2n m-bit words ROM a0a0 a1a1 anan n Address lines d0d0 d1d1 dndn m data lines