1. Package Technology Trends and Lead Free Challenges C. Michael Garner, Fay Hua, Nagesh Vodrahalli, Ashay Dani, Tom Debonis, Raiyo Aspandiar, and Gary Brist Intel Corporation

2. C. Michael Garner Feb. 13, 2005 2 Agenda Technology Trends & Drivers Technology Trends & Drivers Lead Free Lead Free Package Technology Trends Package Technology Trends Lead Free Technology Challenges Lead Free Technology Challenges Summary Summary

3. C. Michael Garner Feb. 13, 2005 3 Key Messages Moore’s Law is alive and well Moore’s Law is alive and well New technologies will require improved materials New technologies will require improved materials The lead free transition is underway The lead free transition is underway Significant technology progress has been made Significant technology progress has been made Lead free challenges remain… Lead free challenges remain…

4. C. Michael Garner Feb. 13, 2005 4 10000 1000 100 10 10 1 0.1 0.01 Micron Nanometer 197019801990200020102020 Nominal feature size Nanotechnology 130nm 90nm 70nm 50nm Gate Width Technology Scaling

5. C. Michael Garner Feb. 13, 2005 5 Intel’s Transistor Research in Deep Nanotechnology Space 65nm process 2005 production 30nm 20nm 45nm process 2007 production 32nm process 2009 production 15nm Experimental transistors for future process generations 22nm process 2011 production 10nm Transistors will be improved for production Source: Intel

6. Delay vs. Technology Generation Data From: Bohr, Mark T; “Interconnect Scaling -The Real Limiter to High Performance ULSI”; Proceedings of the 1995, IEEE International Electron Devices Meeting; pp241-242 Gate wi Cu & Low K Interconnect Will Dominate Timing Cu / Low-k Buys 1-2 Generations What is Required Beyond 0.1u ? Gate w Al & SiO2 Gate 6

7. C. Michael Garner Feb. 13, 2005 7 Source: Intel Copper lines Low k dielectric Transistors New Materials for High Performance Interconnects

8. C. Michael Garner Feb. 13, 2005 8 Lines do not represent any fitting. They are added to help read the data points Lower K ILD Required for Future Technologies Mechanical strength dropping dramatically with lower K Reducing K below 2.4 achieved with pores Mechanical strength dropping dramatically with lower K Reducing K below 2.4 achieved with pores

9. C. Michael Garner Feb. 13, 2005 9 Lead Free

10. C. Michael Garner Feb. 13, 2005 10 Lead Free Transition Lead Free Solders require higher assembly temperatures Lead Free Solders require higher assembly temperatures 50 C 100 C 150 C 200 C 250 C 300 C 63Sn/37Pb 52In/48Sn 58Bi/42Sn 91Sn/9Zn 96.5Sn/3.5Ag 93.6Sn/4.7Ag/1.7Cu 97In/3Ag 99.3Sn/0.7Cu 90Sn/5Sb Binary Systems 95Sn/3.5Ag/1.5In 77.2Sn/20In/2.8Ag 95.2Sn/3.5Ag/0.8Cu/0.5Sb 91.8Sn/4.8Bi/3.4Ag Ternary & Quaternary Systems Castin TM Indalloy 227 Temperature All Compositions in wt% Ag: Silver Bi: Bismuth Cu: Copper In: Indium Sb: Antimony Sn: Tin Zn: Zinc Element Symbols

11. C. Michael Garner Feb. 13, 2005 11 mPGA socket Where’s the Lead? FCPGA CPU Package FCBGA CPU/Chipset Package PC Motherboard Other Packages Containing Lead -Wirebond BGA: Balls -Surface Mount Leaded Pkgs: Leads Pins C4 Bumps Caps Level 1 Interconnects Exempt if high Pb content LEGEND No Lead Description Lead Definition Actives; Passives Balls Level 2 Interconnects C4 BumpsBalls Exempt if high Pb content Board Surface Lead is pervasive through-out an assembled PCB - Replacing this 40+ year old technology must be done cautiously and methodically - Objectives and Background

12. C. Michael Garner Feb. 13, 2005 12 Eliminating the Pb in Intel Components Lead Flip-Chip Ball Grid Array (FC-BGA) PGA socket Flip-Chip Pin Grid Array (FC-PGA) Lead Capacitors Solder Balls Capacitors Flip-Chip Bump Printed Circuit Board Lead Flip-Chip Bump X X X ^RoHS Exempt ^EU approves temporary exemption for Flip Chip Pb-Sn Solder * 95% of the Pb Content Removed from Flip-chip Packages *Percentage based on weight

13. C. Michael Garner Feb. 13, 2005 13 Lead Free Package Early issues were package material high temperature compatibility Early issues were package material high temperature compatibility  Polymers, adhesives, substrates Lead Free solder mechanical properties Lead Free solder mechanical properties Flip Chip lead free solder challenge Flip Chip lead free solder challenge

14. C. Michael Garner Feb. 13, 2005 14 Solder Properties Lower is better Higher is better

15. C. Michael Garner Feb. 13, 2005 15 Intel Lead-free Technology Progress 2001 / 2002 20032004 Wire bond Leadframe & BGA Flip-Chip SLI Wire bond Chip-scale Package Technology TBD Done Flip-Chip FLI SLI: Second Level Interconnect (package-to-board) FLI: First Level Interconnect (die-to-package) 12/04: EU TAC approved exemption for lead in flip-chip FLI Done

16. C. Michael Garner Feb. 13, 2005 16 Product & Package Trends High Integration Package Computing Converged Communication & Computing Converged Communication & Computing High Performance Package Market & Technology are driving new package solutions

17. C. Michael Garner Feb. 13, 2005 17 High Performance Package

18. C. Michael Garner Feb. 13, 2005 18 Flip Chip BGA Package Pb-free Flip-Chip Package Technology Challenges Many Challenges exist to remove the remaining 5% of Lead (Pb) Die Polyimide Substrate Solder Resist Flip-Chip Bump Flip Chip Joint Integrity Silicon Protection Die Under Fill Process Silicon Integration

19. C. Michael Garner Feb. 13, 2005 19 Integrated Assembly Challenges Tin-Lead Solder Profile Reflow @ 183C Peak Temp. = 205 to 220C Lead Free Solder Profile Reflow @ 217C Peak Temp = 235 to 245C Time in Minutes Temperature, Deg C At room temperature The Package shrinks more than the chip Intel continues to work with the Industry to develop new technologies that meet performance and reliability requirements needed to complete the transition to lead-free (if possible) HeatingCooling At reflow temperature Silicon Chip High lead Flip Chip Bump Package (Copper Laminate) Typical Assembly Reflow Profile

20. C. Michael Garner Feb. 13, 2005 20 High Integration Packages

21. C. Michael Garner Feb. 13, 2005 21 High Integration Packages 4 Die Stack with Large Overhang Substrate 1.5mm Die Attach Adhesive Adhesion (Low T cure) Shrinkage Cure Temperature Modulus Tg Moisture Absorption Thickness Die Attach Adhesive Adhesion (Low T cure) Shrinkage Cure Temperature Modulus Tg Moisture Absorption Thickness Molding Compound CTE Local CTE Adhesion Moisture Absorption Future Thermal Conductivity Low Stress Molding Compound CTE Local CTE Adhesion Moisture Absorption Future Thermal Conductivity Low Stress Technology Trends More chips per package Thinner chips, adhesive & substrate Lead Free All materials must be stable with 260C board assembly Technology Trends More chips per package Thinner chips, adhesive & substrate Lead Free All materials must be stable with 260C board assembly

22. C. Michael Garner Feb. 13, 2005 22 BGA Challenge

23. C. Michael Garner Feb. 13, 2005 23 BGA Solder Ball Trend BGA size may accentuate Lead Free mechanical properties BGA size may accentuate Lead Free mechanical properties

24. C. Michael Garner Feb. 13, 2005 24 Laminate Substrates & Printed Wiring Boards

25. C. Michael Garner Feb. 13, 2005 25 Performance Signaling Advanced metrology Non-Cu medium? ~20GTs Higher frequencies require higher I/O performance Higher frequencies require higher I/O performance point-to-point ~10GTs +advanced pkg/IO 2GTs +differential Challenges

26. C. Michael Garner Feb. 13, 2005 26 Laminate Material Laminate Material  Insignificant change in electrical properties  FR-4 laminate acceptable except for High Layer count (18 Layers or more) and thick boards (0.093 inches or more)  Via hole integrity as via hole plating has tendency to crack for thicker boards as Z- axis expansion is greater at Peak Reflow Temperatures (PRT) for Lead free then compared to SnPb Large Size boards (12 inches x 15 inches) need support frame during reflow soldering Large Size boards (12 inches x 15 inches) need support frame during reflow soldering Expansion in the Z Axis Temperature Tg Z axis X axis Barrel plating Crack PRT SnPb PRT SnAgCu Board Laminate Considerations for Lead Free Soldering

27. C. Michael Garner Feb. 13, 2005 27 Processing & Use Thermal Mechanical Challenge Via Reliability Concerns Via Reliability Concerns  260C Board Assembly (> 0.07” thick boards)  Max Operating Temps >130C  Thermal Cycle Stress  Modulus vs Temperature  CTE vs Temperature  Adhesion vs Temperature  Toughness Grade A Grade B Grade C Flexural Strength (Grain) at Elevated Temperature Absolute (Thousand PSI) 0 10 20 30 40 50 60 70 80 90 100 25456585105125145165185 Temperature (Celsius) Grade D Interconnect: Barrel And Post Interconnect: Barrel And Post

28. C. Michael Garner Feb. 13, 2005 28 Challenges Summary Packages must be compatible with 250- 260C assembly Packages must be compatible with 250- 260C assembly Flip Chip solder requirements are very complex Flip Chip solder requirements are very complex BGA trend to smaller size may be more challenging BGA trend to smaller size may be more challenging Thick lead free assembly challenging for thick PCBs Thick lead free assembly challenging for thick PCBs

29. C. Michael Garner Feb. 13, 2005 29 Key Messages Moore’s Law is alive and well Moore’s Law is alive and well New technologies will require improved materials New technologies will require improved materials The Lead Free transition is underway The Lead Free transition is underway Significant lead free technology progress has been made Significant lead free technology progress has been made Significant lead free challenges remain… Significant lead free challenges remain…

30. C. Michael Garner Feb. 13, 2005 30 For further information on Intel's silicon technology and Moore’s Law, please visit the Silicon Showcase at www.intel.com/research/silicon

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