1. PowerBench Programmable Power Supply Dror Lazar Moran Fishman Supervisor: Boaz Mizrahi Winter Semester 2009/10 HS DSL

2. Project Overview - Reminder A versatile power supply unit with multiple outputs for laboratory use and testing of various electronic devices.

3. Active load Power supply Control unit User interface for standalone operation LCDKeysLEDs User interface DUTDUT Measurement unit Overview A brief reminder Overview A brief reminder

4. DC-DC Converter Post regulator ADC Voltage Sense DAC Current Sense Output FPGA Controller Block & Registers Output setting Input voltage sense feed- forward Tempe- rature Current limit PWM Microprocessor Overview Control Scheme ADC Auxiliary Voltage Sense Overview Control Scheme

5. Implementation 1) System & Board design (2 semesters)– completed 3 separate boards : - “Digital” – control board - “Analog” – sink/source/measurement (SSM) - “Panel” – user interface (UI) 2) Hardware bring-up & FPGA design (semester) – our project - Analog board bring-up, Digital board power-path debug - FPGA design : A/D & D/A interfaces, PWM, SMPS controllers - PC –> Cypress –> PIC basic implementation - PIC – FPGA interface 3) Software design (semester) – another project - PIC microprocessor software - Cypress USB controller software - PC drivers and applications

6. - Buck converters - Buck converters A/Ds - LDOs - LDOs D/As - LDOs A/Ds - Cuk converter - Cuk converter A/D - Source operation : - Full-path bring-up : PC  USB  PIC  FPGA  Bucks / Cuk  LDOs  DUT - PWM duty-cycle step response with various loads connected to LDOs outputs - Load operation : - FPGA configures path to load mode. - FPGA configures load-circuit D/A to constant current sink. - connecting laboratory power supply, checking current sink. - changing current sink amount – checking step response. Analog Board Bring-Up

7. 2 control loops : Bucks / Cuk control loop LDOs control loop implement controller using SMPS controller design principles. integrate with A/D & D/A interfaces in FPGA check controller performance : step response, O.S, settling time FPGA Controller Design PC – PIC – FPGA Interface Design designing communication protocol to PIC microprocessor using SPI interface (registers in FPGA) implementing basic software in PC & PIC – different scenarios in Source & Load modes. check FPGA measurements from A/Ds in both modes with PC software

8. Timetable 4/3 11/3 18/3 25/3 1/4 8/4 15/4 22/4 29/4 6/5 13/5 20/527/5 3/6 10/6 17/6 24/6 1/7 8/7 END System introduction Verilog learning Design FPGA Modules req. for Bucks bring-up Mid semester Presentation Final Presentation Char. Presentation FPGA modules simulations FPGA configuration- Bucks,4-ch A/D Bring up Design FPGA Modules for LDOs bring-up Digital board Power path debug FPGA configuration- LDOs,2-ch A/D,D/A Bring up Full path debug – Source operation Negative channel Bring up (Cuk) Full path debug – Load operation SMPS controller Design – 2 loops PIC – FPGA Interface design

9. Questions ?