2. Subwavelength Design: Lithography Effects and Challenges Part II: EDA Implications Andrew B. Kahng, UCLA Computer Science Dept. ISQED-2000 Tutorial March 20, 2000

3. Forcing Trends in EDA Silicon complexity and design complexity –many opportunities to leave major $$$ on the table –issues: physical effects of process, migratability –design rules more conservative, design waivers  –device-level layout opts in cell-based methodologies Verification cost increases dramatically Prevention a necessary complement to checking Successive approximation = design convergence –upstream activities pass intentions, assumptions downstream –downstream activities must be predictable –models of analysis/verification == objectives for synthesis

4. EDA Awareness of Process EDA wants to know as little as possible This part of tutorial: the unavoidable issues

5. Necessary Formulations, Flows Upstream objectives want to capture downstream layout operations “transparently” New problem formulations –PSM: more global phenomena, scalability issues –OPC: mostly local phenomena –function-driven corrections –hierarchical and reuse-centric regimes New tool integrations

6. Phase Smart Custom Layout

7. Phase Smart Place and Route

8. Phase Smart Verification

9. Global phenomena in PSM phase layout

10. Phase Assignment in PSM Features Conflict areas (<B) 00180 < B > B Assign 0, 180 phase regions such that: (dark field) feature pairs with separation < B have opposite phases (bright field) features with width < B are induced by adjacent phase regions with opposite phases b  minimum separation or width, with phase shifting B  minimum separation or width, without phase shifting  b (Dark field, neg resist)

11. Conflict Graph < B Vertices: features (or phase regions) Edges: “conflicts” (necessary phase contrasts) (feature pairs with separation < B )

12. Odd Cycles in Conflict Graph Self-consistent phase assignment is not possible if there is an odd cycle in the conflict graph Phase-assignable  bipartite  no odd cycles 0 phase180 phase ??? phase

13. Breaking Odd Cycles  B Must change the layout: change feature dimensions, and/or change spacings PSM phase-assignability is a layout, not verification, issue

14. blue features green 180-shift black boundaries b/w 0 and 180 areas (to be deleted) red odd degree Bright-Field (Positive-Resist) Context Every critical-width feature defined by opposite-phase regions Regions not defined a priori

15. Value Proposition to Designers 0.10  m feature sizes in production in 1999 –  2x performance –Higher yield –“Transparent” to designer

16. Problem Statements I Develop efficient algorithms for minimum-cost phase region definition and phase assignment in bright-field context –open: definition of cost (mfg difficulty, area, …) Continuum between sparse, dense criticality –DF Alt PSM + BF binary trim mask approach simple and elegant for sparse critical features –what about when all features are critical? (full-chip area opt, in addition to gate shrink) –can be treated as a routing problem (of phase edges)

17. Problem Statements II New logic (mapping) and performance optimization formulations –with phase shifting, gate lengths and wire widths continuously variable between b and B –without phase shifting, gate lengths and wire widths must be at least B –not all features can be phase-shifted: function-driven What is optimal choice of phase-shifted features, and their sizes?

18. Problem Statements III Understand PSM implications for custom layout –define a taxonomy of phase conflict –no set of traditional design rules can handle all phase conflicts  what are “good layout practices”? “no T’s on poly” “fingered transistors should have even-length fingers” etc. Address PSM as a multi-layer problem –e.g., conflict can be solved by re-routing a connection to another layer

19. Layer Assignment

20. Local phenomena in OPC

21. Problem Statements IV Pass functional intent down to OPC insertion –OPC insertion is for predictable circuit performance, function –Problem: make only corrections that win $$$, reduce perf variation (i.e., link to performance analysis, optimization) ? Pass limits of mask verification up to layout –Problem: avoid making corrections that can’t be manufactured or verified

22. Problem Statements V Minimize data volume –Problem: make corrections that win $$$, reduce perf variation up to some limit of data volume for resulting layout (== mask complexity, cost) Layout needs models of OPC insertion process –Problem: taxonomize implications of layout geometry on cost of the OPC that is required to yield function or “faithfully” print the geometry –find a realistic cost model for breaking hierarchy (including verification, characterization costs)

23. Hierarchical and Reuse-Centric Contexts

24. Issues Raised by Hierarchy, Reuse Large data volume and verification costs when hierarchy is broken -- but PSM and OPC are both context-dependent! Standard-cell approach requires absolute composability of cells -- this must somehow be guaranteed as we move into PSM regime

25. Problem Statements VI Given a cell library, what is its flexibility (i.e., composability with respect to PSM) ? Given a standard-cell layout and allowed increase in hierarchical layout data volume, what is the maximum reduction in area obtainable by creating new cell masters with different phase layout solutions? Given a standard-cell layout with phase-solution instantiations that induce conflicts, what is minimum- cost removal of phase conflicts? –DOF’s: change instance, shift, space, mirror,...

26. Integrated Layout Flow, 1 Gate-level netlist, performance constraint budgeting, early context (mask/litho technology, area density...) Standard-cell placement with integrated compatibility awareness (composable PSM layouts) Global and detailed routing, cell resynthesis on fly –delay, noise, reliability assumptions = constraints –OPC- and PSM-aware min-cost layout synthesis subject to constraints (e.g., minimize costs of breaking hierarchy, follow “good practices”, etc.) –fill abstractions (for parasitic extraction) in constraint- driven routing

27. Integrated Layout Flow, 2 Density analysis, CMP-fill estimation based on detailed routing Post-detailed routing performance analysis PSM phase assignability check for all layers –new compaction constraints as necessary –layout compaction or incremental detailed routing –until pass phase assignability, performance analysis –note: integration with full-chip geometric compaction! Actual dummy fill insertion –issues: data volume

28. Integrated Layout Flow, 3 Detailed physical verification (geom, conn, perf) Full-chip OPC insertion –issues: min-cost OPC that achieves required function –issues: data volumes, metrics, intermediate formats –issues: tools stepping on each other (line extensions in DSM router rules are “zeroth-order OPC”, for example) Full-chip printability check Silicon-level DRC/LVS/performance analysis

29. Conclusions New problem formulations –PSM: layout practices, automated full-chip and standard-cell compatible solutions –OPC: taxonomy of local phenomena, data reduction –function-driven corrections (can filter complexity) –hierarchy, data volume, reuse concerns New tool integrations –compaction, on-the-fly cell synthesis, incremental detailed routing –graph-based (verification-type) layout analyses –new performance opts, even logic opts

30. Example Details I: Automatic Conflict Resolution

31. Compaction-Oriented Approach Analyze input layout Determine constraints for output layout –new PSM-induced (shape, spacing) constraints Compact (e.g., solve LP) with min perturbation objective –e.g., minimize sum of differences between old and new positions of each edge Key: Minimize the set of new constraints, i.e., break all odd cycles in conflict graph by deleting a minimum number of edges.

32. One-Shot Phase Assignment conflict graph compaction phase assignment find min-cost edge set to be deleted for 2-colorability

33. Conflict Graph Dark Field: build graph over feature regions edge between two features whose separation is < B Bright Field: build graph over shifter regions two edge types adjacency edge between overlapping phase regions : endpoints must have same phase –essentially, these regions must be “merged” into single phase shifter –DRC-like (gap, notch type) local rules must likely be applied to such “merging” conflict edge between shifters on opposite side of critical feature: endpoints must have opposite phase Step 3: simple reduction to previous (dark-field) T-join solution: each dotted edge becomes a 2-chain (introduce one extra vertex)

34. Conflict Graph Dark Field: conflict graph G green = feature; red = conflict Bright Field: conflict edge adjacency edge conflict graph G

35. Conflict Graph for Cell-Based Layouts Coarse view: at level of connected components of conflict graphs within each cell master each of these components is independently phase-assignable can be treated as a single “vertex” in coarse-grain conflict graph edge in coarse-grain conflict graph cell master Acell master B connected component

36. Detail: Conflict Edge Weight Conflict edges not on critical path: break for free Or, use min-perturbation objective critical path

37. F4 F2 F3 F1 S1 S2 S3 S5 S4 S6 S7S8

38. Black points - shifters Blue - shifter overlap Thick edges - critical Bipartization Problem: delete min # of thin edges to make graph bipartite

39. Black points - features Blue - shifter overlap Pink - extra nodes to distinguish opposite shifters Bipartization Problem: delete min # of nodes (or edges) to make graph bipartite

41. Black points - shifters Blue - shifter overlap Thick edges - critical Bipartization Problem: delete min # of thin edges to make graph bipartite

42. Black points - features Blue - shifter overlap Pink - extra nodes to distinguish opposite shifters Bipartization Problem: delete min # of nodes (or edges) to make graph bipartite

43. Key Technique: Reduction to T-join Goal: delete minimum-cost set of edges from conflict graph G, so as to eliminate odd cycles Construct geometric dual graph D = dual(G) Find odd-degree vertices T in D Solve the T-join problem in D: –find min-weight edge set J in D such that all T-vertices have odd degree w.r.t. J all other vertices have even degree w.r.t. J Solution J corresponds to the desired min-cost edge set in conflict graph G

44. Optimal Odd Cycle Elimination conflict graph G dual graph D T-join of odd-degree nodes in D dark green = feature; red = conflict

45. Optimal Odd Cycle Elimination corresponds to broken edges in original conflict graph - assign phases: dark green and purple - remaining red conflicts correctly handled T-join of odd-degree nodes in D dark green = feature; red = conflict

46. T-join Problem in Sparse Graphs Reduction to matching –construct a complete graph T(G) vertices = T-vertices edge costs = shortest-path cost –find minimum-cost perfect matching Typical example = sparse (not always planar) graph –note that conflict graphs are sparse –#vertices = 1,000,000 –#edges  5  #vertices –# T-vertices  10% of #vertices = 100,000 Drawback: finding all shortest paths too slow and memory-consuming –#vertices = 100,000  #edges = 5,000,000,000

47. T-join Problem: Reduction to Matching Desirable properties of reduction to matching: –exact (i.e., optimal) –not much memory (say 2-3Xmore) –results in a very fast solution Solution: gadgets! –replace each edge/vertex with gadgets s.t. matching all vertices in gadgeted graph  T-join in original graph

48. T-join Problem: Reduction to Matching replace each vertex with a chain of triangles one more edge for T-vertices in graph D: m = #edges, n = #vertices, t = #T in gadgeted graph: 4m-2n-t vertices, 7m-5n-t edges cost of red edges = original dual edge costs cost of (black) edges in triangles = 0 vertex in T vertex  T

49. Example of Gadgeted Graph Dual Graph Gadgeted graph black + red edges == min-cost perfect matching

50. Results Runtimes in CPU seconds on Sun Ultra-10 Greedy = breadth-first-search bicoloring (similar to Ooi et al.) GW = Goemans/Williamson95 heuristic Cook/Rohe98 for perfect matching Latest improved gadgets: runtimes decrease by factor of 6

51. Example Details II: Auto-P&R Flow Issues

52. Constraints PSM must be “transparent” to ASIC auto-P&R –“free composability” is the cornerstone of the cell-based methodology! –focus on poly layer  we are concerned with placer, not router Competitive context for placer –extremely competitive runtime regimes (e.g., 10 6 cells detail-placed in 20 min); faster runtimes needed in RTL-planning methodologies (Nano/PKS, Tera) –any nontrivial cost of checking placement phase-assignability is unacceptable Iteration between placer and a separate tool is unacceptable –interface to auto-P&R tools is bulky (e.g., 100s of MB for DEF), slow –no known convergent method for post-P&R phase-assignability checks to drive P&R to guaranteed correct solution (very difficult!) P&R tool MUST deliver guaranteed phase- assignable poly layer

53. Guidelines Placer –no re-entry into placer from an external tool any needed extra functionality must be built directly into placer –placer must guarantee a phase-assignable poly when finished –polygon layout information currently not in placement vocabulary available relevant abstractions: pin EEQs/LEQs, overlap layer geometries side files or LEF extensions needed for, e.g., capturing versioning or phase shifters near left/right cell boundaries Cell layout –cell layouts and phase shifters are assumed fixed during library creation on-the-fly cell layout synthesis or layout perturbations generally not allowed –2 k’ possible versions (i.e., distinct phase bindings) are available for a given master cell with k connected components in its phase conflict graph, k’ < k of which contain critical poly at cell boundary impractical to use EEQs to capture versioning within iterative improvement

54. Types of Composability Same-row composability –any cell can be placed immediately adjacent (in the same row) to any other cell Adj-row composability –any cell can be placed in an adjacent cell row to any other cell, with the two cells having intersecting x-spans Four cases of cell libraries (G = guaranteed; NG = not guaranteed) –Case 1: adj-G, same-G most-constrained cell layout; most transparent to placer –Case 2: adj-G, same-NG –Case 3: adj-NG, same-G –Case 4: adj-NG, same-NG least-constrained cell layout; least transparent to placer

55. Case 2: Adj-G, Same-NG Blue vertices, edges = graph of phase assignment “dependencies”

56. Case 3: Adj-NG, Same-G Blue vertices, edges = graph of phase assignment “dependencies”

57. Case 4: Adj-NG, Same-NG Blue vertices, edges = graph of phase assignment “dependencies”

58. Overlap Layer Abstraction in LEF Like “teeth of a broken comb” defined for each master cell Placer makes sure that the teeth don’t collide when the cells are placed, i.e., the two “broken combs” interlace Available today in LEF standard; placer understands overlap layer –current heuristics may not scale well if many instances have overlap geometry Traditional picture of overlap geometries

59. Case 1: Adj-G, Same-G Solution 1: “no restrictions on the cell layout” – create cell abstractions such that placer runs in “normal” mode e.g., pre-bloat (by 1 site) cells that have critical poly near left/right boundary e.g., create overlap layer obstacles corresponding to critical poly near top/bottom boundary Solution 2: smart rules to restrict cell layout –e.g., every pair of boundary-CP features from the same cell must be non-interfering definition: two features are non-interfering if they are in different connected components of the cell’s phase conflict graph –no boundary-CP feature is “near” two different sides of its cell –these two restrictions  composability guaranteed (no odd cycles possible) Solution 3: dumb rules to restrict cell layout –all cells have 250nm-wide 0-phase boundary (IBM-style AltPSM)

60. Notation M = number of master cells in library C i = i th master cell, i = 1, …, M w i = width of i th master cell, i = 1, …, M V i = number of versions of the i th master cell, i = 1, …, M C ik = k th version of i th master cell, i = 1, …, M; k = 1, …, V i N = number of movable cells in the row of interest R h = h th cell in the row of interest S h = master cell corresponding to h th cell in row of interest boundary-CP = critical poly feature “near” the cell boundary

61. Cases 2,4: Same-NG Each (sub)row checked separately, post-placement Basic tool: cell compatibility table –library is precharacterized by M 2 two-dimensional arrays A ij, one array for each possible pairing of cells with C i to the left of C j –A ij = minimum site separation at which C ip can be placed adjacent to C jq (p = 1, …, V i and q = 1, …, V j ) example: M = 500 with 16 versions of each master cell  < 30 MB storage Goals: (1) if phase assignment possible, return set of versions for each of the cell instances (2) if not possible, return set of versions plus set of inserted feedthroughs (extra sites) such that minimum perturbation is achieved

62. Cases 2,4: Same-NG Example Sol’n Shortest-path finding in a simple graph (actually, a DAG) : –for each version j of each cell R i, create node, i = 1, …, N and j = 1, …, V r i –create source node and termination node –create directed edges (, ) for all versions j of cell R i and versions k of cell R i +1 (weight = cost of perturbing placement to achieve minimum allowed site separation) –create zero-weight directed edges (, ) for all versions j of cell R 1 and (, ) for all versions j of cell R N Minimum-perturbation solution (specifies compatible versions as well as required changes in cell positions) given by shortest path from to

63. Cases 3,4: Adj-NG Example Sol’ns Basic cause of problem: horizontal poly near shared rails –complex cells that push the cell height (#pitches), e.g., latch/FF, adder, mux Solution 1: partial amelioration by layout constraints –e.g., for horizontal critical poly near power rail, the outside shifter must be 0-phase (NTI style) –can be done silently by version compatibility, etc. Solution 2: abstract w/existing LEF overlap layer construct

64. Conclusions (again) New problem formulations –PSM: layout practices, automated full-chip and standard-cell compatible solutions –OPC: taxonomy of local phenomena, data reduction –function-driven corrections (can filter complexity) –hierarchy, data volume, reuse concerns New tool integrations –compaction, on-the-fly cell synthesis, incremental detailed routing –graph-based (verification-type) layout analyses –new performance opts, even logic opts Non-trivial flow, methodology effects span library creation to auto-P&R, performance optimization, etc.