1. 1 Enhancing Performance of Iterative Heuristics for VLSI Netlist Partitioning Dr. Sadiq M. Sait Dr. Aiman El-Maleh Mr. Raslan Al Abaji. Computer Engineering Department King Fahd University of Petroleum & Minerals

2. 2 Introduction Problem Formulation Cost Functions PowerFM Experimental Results Conclusion Outline ….

3. 3 Technology0.1 um Transistors200 M Logic gates40 M Size520 mm 2 Clock2 - 3.5 GHz Chip I/O’s4,000 Wiring levels 7 - 8 Voltage0.9 - 1.2 Power160 Watts Supply current~160 Amps Performance Power consumption Noise immunity Area Cost Time-to-market Tradeoffs!!! The VLSI Chip in 2006

4. 4 Decomposition of a complex system into smaller subsystems Each subsystem can be designed independently speeding up the design process (divide-and conquer-approach) Decompose a complex IC into a number of functional blocks, each of them designed by one or a team of engineers Decomposition scheme has to minimize the interconnections between subsystems Why we need Partitioning ?

5. 5 System Level Partitioning Board Level Partitioning Chip Level Partitioning System PCBs Chips Sub-circuits/Blocks Levels of Partitioning

6. 6 Partitioning Algorithms Group Migration Simulation Based Iterative Performance Driven 1.Kernighan-Lin 2.Fiduccia- Mattheyeses (FM) 3.Multilevel K-way Partitioning Others 1.Simulated annealing 2.Simulated evolution 3.Tabu Search 4.Genetic 1.Lawler et al. 2.Vaishnav 3.choi et al. 4.jun’ichiro et al. 1.Spectral 2.Multilevel Spectral Classification of Partitioning Algorithms

7. 7  Objective: Design a class of iterative algorithms for VLSI multi objective partitioning optimizing Power AND Delay AND Cutset  Constraint: Balanced partitions to a certain tolerance degree (10%) Problem formulation

8. 8 Based on hypergraph model H = (V, E) c(e) = 1 if e spans more than 1 block Cutset = sum of hyperedge costs cutset = 3 Cutset

9. 9 Delay Gate delay: d(v) Constant inter-chip wire delay d c : Path delay between nodes v i and v j as d(p ij ) Number of nodes cut along path p ij as ncut(p ij ) Objective:

10. 10 The average dynamic power consumed by CMOS logic gate in a synchronous circuit is given by: Ni : is the number of output gate transitions per cycle ( switching Probability) : is the Load Capacitance Power

11. 11 : Load Capacitances driven by a cell before Partitioning : additional Load due to off chip capacitance.( cut net) Total Power dissipation of a Circuit: Power

12. 12 : Can be assumed identical for all nets :Set of Visible gates Driving a load outside the partition. Power

13. 13 The Balance as a constraint is expressed as follows: However balance as a constraint is not appealing because it may prohibit lots of good moves. Objective : |Cells(block1) – Cells(block2)| Balance

14. 14 A good partitioning can be described by the following fuzzy rule IF solution has small cutset AND low power AND short delay AND good Balance. THEN it is a good solution Fuzzy Cost Function

15. 15 The above rule is translated to AND-like OWA Represent the total Fuzzy fitness of the solution, our aim is to Maximize this fitness. Respectively (Cutset, Power, Delay, Balance ) Fitness. Fuzzy cost function

16. 16 WhereO i and C i are lower bound and actual cost of objective “i”  i (x) is the membership of solution x in set “good ‘i’ ” g i is the relative acceptance limit for each objective. Membership functions

17. Start with a balanced partition P = {X, Y}. Repeat For i = 1 to n: Choose a free cell b  X  Y s.t. moving b to the other side gives the highest Power gain, Pgain(b), and moving b preserves balance in P. Move and lock b. Let g i = gain(b). Find k s.t. G = g 1 + g 2 + ….. + g k is maximized and move the k cells to their complement partitions Until G = 0 PowerFM- Algorithm

18. abcabc defdef acac defdef b locked acac dfdf be acac f b e d g1g1 g2g2 g3g3 g4g4 An Example

19. 19 c f b e d g5g5 a f b e d g6g6 a c b e d a cf If G = g 1 + g 2 + g 3 + g 4 is the largest partial sum, the final partition after this pass is: cdecde afbafb An Example

20. 20 Power Gain Calculation Xi: is the set of cut critical nets. Ui: is the set of uncut critical net.

21. 21 Experimental Results ISCAS 85-89 Benchmark Circuits

22. 22 PowerFM Vs SimE For Power For bigger circuits the performance is degraded.

23. 23 GA from PowerFM vs Random Start

24. 24 TS from PowerFM vs Random Start

25. 25 Conclusion Proposed a modification to the FM algorithm, PowerFM, targeting low power. PowerFM results are comparable to SimE but with a faster runtime. Investigated the use of PowerFM as a starting solution to iterative algorithms, GA and TS. GA performed significantly better when starting from PowerFM.