1. Verilight Adam S. Waksman Richard A. Sampson Chisom N. Maduike Malcolm T. Bressendorf Albert L. Jimenez

2. Background on HDLs Formal description of digital logic – Verilog, VHDL, Bluespec Complete Parallelism Convert directly to hardware – Execute on FPGA – Fabricate physical chip Fujitsu

3. Computer Architecture Lab Block Diagram Source Code NetlistFPGA Coding HDLs: Design Process Synthesis Compilation

4. Why People Hate HDLs “I have checked out a ton of different HDLs and why does every single one of them require a lot of code to do 1 thing, and why is their syntax so radically different from everything that exists for regular programming?” -XKCD Forums User

5. Why People Hate HDLs “I have checked out a ton of different HDLs and why does every single one of them require a lot of code to do 1 thing, and why is their syntax so radically different from everything that exists for regular programming?” -XKCD Forums User

6. Salvation through Abstraction Analogy: OpenGL – Abstracted away pixels and points – Libraries and Objects – Simple code for what users want Verilight – Abstracted away wires and registers – Simple code for synchronous digital logic design Microprocessors Peripherals IP Units

7. Abstraction and Expressiveness module pc_module(clk, nrst, pc_out); input clk; input nrst; output [31:0] pc_out; reg [31:0] pc; wire [31:0] pc_val; wire [31:0] sum; assign sum = pc_val + 32'b100; assign pc_val = pc; assign pc_out = pc_val; always @(posedge clk) begin if(nrst == 1'b0) begin pc <= 32'b0; end if(nrst == 1'b1) begin pc <= sum; end endmodule define combo pc_template: pc = pc + 4; pc_out = pc; specify pc = pc_template(pc=32);

8. Features Object Orientation – Combo/Arch – Templates/Polymo rphism Block Diagrams – Syntax forces block structure – Scope maintained throughout a block Code Analysis – Semantically meaningful blocks – Automated Stat Tracking Motivation: Intel PTU – Automated Testing Stimulus/GTK Wave – Dynamic Hardware Assertions For debugging and verification Motivation: HOST specify two_adders = adder(2); define arch MyCoolArch: in → two_adders; two_adders → ff → divider; divider → ff → out; count divider in DivCount; count two_adders in AddCount; assert DivCount == AddCount;

9. Compiler Tools and Architecture

11. Computer Architecture Lab Informal Verification – Waveform viewer – Simulation on Quartus – Textual Analysis using scripts Formal Verification – Programming Language Interface (PLI) Interface between generated Verilog code and a model written in C Verification

12. Computer Architecture Lab Verification: PLI

13. Lessons Learned Languages – A lot more to it than we thought – Many layers HDLs – Can be made simpler, more abstract Team Delegation – Teamwork important – Hard to orchestrate clashing schedules

14. Questions