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Performed by: Alex Shpiner Eyal Azran Instructor: Boaz Mizrachi המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי.

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Presentation on theme: "Performed by: Alex Shpiner Eyal Azran Instructor: Boaz Mizrachi המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי."— Presentation transcript:

1 Performed by: Alex Shpiner Eyal Azran Instructor: Boaz Mizrachi המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering Enhanced Network Interface Card using FPGA Spring 2004 1

2 Abstract המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 Enhanced implemention of Network interface card using FPGA chip, which creates echo request packets upon given parameters, and sending them to the network, and creates echo reply packets when identify request packet received by the card. A driver to control the above features by software is also supplied.

3 System description המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 The communication board connects to a PCI slot on the mother board. A PCI bridge converts the PCI bus to the simpler local bus protocol which is used to connect to the FPGA. All requests from the dedicated driver either refer to the inner PCI bridge registers or are passed for the FPGA. The FPGA then analyze the request, builds an Echo request packets and transmit them on the network. The destination station replies the requests. Statistics about the process are collected and passed to the user via the driver.

4 Specification המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Hardware Software 4 Full control over the card via the driver. The Driver was developed using WinDriver. VHDL modules implements the above design on the FPGA chip.

5 System Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5 FPGA PLXPLX MACMAC PHYPHY PCIPCI ETHERNETETHERNET - Data Flow - Control Signals

6 FPGA Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 MACMAC CIFCIF TRN RCV ARB Shared bus TRP RCP PLXPLX


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