1. המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering Final Presentation (part A) Performed by: Volokitina Irina, Cohen Ido Instructor: Rivkin Ina Signal Processing on FPGA

2. Agenda Project goals DVI overview Hardware overview Software overview Implementation Demonstration

3. Goals To assimilate GIDEL system PROCWizard tool. Learn how DVI and TMDS works Learn how to use PROCStar II Transferring video data we get from the PC Graphic controller to Display through PROCStar II PSDB DVI

4. Why DVI ?

6. DVI DVI is accepted standard for transferring serially uncompressed digital data at high speeds between a PC host and a digital display, such as an LCD monitor. DVI enables a video signal to be transferred from a PC source to a digital display in its native digital form, simplifying the way PCs communicate with displays and improving display image quality.

7. Why DVI? Before DVI was accepted : Plug & Display (P&D)- expensive connector and provided no dual-link option. Digital Flat Panel (DFP)- offered no analog support and no dual-link option or upgrade path for faster speeds.

8. DVI advantages : Offers analog support through pins on the host side connector,which eliminates the need for a redundant VGA analog conection Available in a dual-link option, providing an upgrade path for even higher-level resolutions Cross compatible with P&D and DFP via mechanical dongle connector

9. TMDS Transition Minimized Differential Signaling

15. GIDEL’S HARDWEAR

16. PROCStar II

19. PSDB PROCStar II and PROCSpark II boards were designed to work with daughterboards. A number of connectors located on the component side of the PROC motherboards enable connecting several daughterboards to these motherboards. These daughter boards are called PSDB. PSDBs can be used for system adaptation and to add logic.

20. PSDB_DVI PSDB_DVI is a type 1 PSDB. This means that it uses a single connector to connect to the PROC motherboard. On the PROC boards, this connector is located to the left of the target FPGA. PSDB_DVI is designed to provide a Digital Video Interface (DVI) connection to the PROC motherboard via its panel. Therefore, this daughterboard is intended to be placed on location 1 when possible. Nevertheless, it will work properly when connected to any other location on the PROC board.

21. PSDB_DVI Connections' Block Diagram Graphic Controller Display

22. RECEIVER SiI1171

23. Block diagram

24. Transmitter SiI1172

25. Block diagram

26. GiDEL PROCWizard tool GiDEL PROCWizard is a hardware-software integration application that was designed to simplify the project development task. Enables the user to rapidly build a design that may be automatically translated into HDL and C++ code Enables the developer to test and debug the design in the PC environment. PROCWizard main features include :

27. GiDEL PROCWizard tool

31. QuartusII tool

32. SiI1172 ports --****************************************************************************************** --* COMPANY : Technion * --* NAME : Diglab * --* BOARD : PROCStarII180-4 * --* IC# : 1 * --* Created : Thu Nov 23 13:03:59 2006 * --* This file was generated by PROCWizard Application version 7.12 * --* Copyright (C) 2006. All Rights Reserved to GiDEL Ltd * --****************************************************************************************** --====================================================================== --= DVI Transmitter connections (on PSDB_DVI) = --====================================================================== data_tx : OUT STD_LOGIC_VECTOR( 11 DOWNTO 0 ); -- Transitter data output msen_tx : IN STD_LOGIC; -- Monitor Sense pd_tx : OUT STD_LOGIC; -- Power Down (Active Low) de_tx : OUT STD_LOGIC; -- Data Enable hsync_tx : OUT STD_LOGIC; -- Horizontal Sync vsync_tx : OUT STD_LOGIC; -- Vertical Sync scl_tx : INOUT STD_LOGIC; -- I2C Clock sda_tx : INOUT STD_LOGIC; -- I2C Data idck_tx : OUT STD_LOGIC; -- Transmitter data clock isel_rst_tx : OUT STD_LOGIC; -- I2C Interface Select ctl3_tx : OUT STD_LOGIC; -- Transmitter Control Signal

33. SiI1171 ports --====================================================================== --= DVI Receiver connections (on PSDB_DVI) = --====================================================================== qe_rx : IN STD_LOGIC_VECTOR( 23 DOWNTO 0 ); -- Receiver even data input qo_rx : IN STD_LOGIC_VECTOR( 23 DOWNTO 0 ); -- Receiver odd data input odck_rx : IN STD_LOGIC; -- Receiver data clock scdt_rx : IN STD_LOGIC; -- Sync detect ctl1_rx : IN STD_LOGIC; -- Receiver control signal ctl2_rx : IN STD_LOGIC; -- Receiver control signal ctl3_rx : IN STD_LOGIC; -- Receiver control signal stag_out_rx : OUT STD_LOGIC; -- Staggered Output pixs_rx : OUT STD_LOGIC; -- Pixel Select st_sda_rx : INOUT STD_LOGIC; -- I2C Data / Output Drive pd_rx : OUT STD_LOGIC; -- Power Down hs_djtr_rx : OUT STD_LOGIC; -- Horisontal Sync De-jitter ock_inv_scl_rx : INOUT STD_LOGIC; -- ODCK Polarity / I2C Clock mode_rx : OUT STD_LOGIC; -- Mode Select hsync_rx : IN STD_LOGIC; -- Horizontal Sync vsync_rx : IN STD_LOGIC; -- Vertical Sync de_rx : IN STD_LOGIC; -- Data Enable pdo_rx : OUT STD_LOGIC; -- Output driver power down hpd_rx : IN STD_LOGIC

34. SiI1171 and SiI1172 configuration --DVI Transmitter connections (on PSDB_DVI) pd_tx <= '1';-- de_tx <= de_rx;-- hsync_tx <= hsync_rx;-- vsync_tx <= vsync_rx;-- scl_tx <= '0';-- sda_tx <= '0';-- idck_tx <= odck_rx;-- isel_rst_tx <= '0';-- ctl3_tx <= '0';-- --DVI Receiver connections (on PSDB_DVI) stag_out_rx <= '1';-- pixs_rx <= '0';-- st_sda_rx <= '1';-- pd_rx <= '1';-- hs_djtr_rx <= '1';-- ock_inv_scl_rx <= '0';-- mode_rx <= '1';-- pdo_rx <= '1';-- AA(0) <= scdt_rx ; --Data enable check Settings for using default DVI Transmitter operation mode not programmable - with no I2C involve samples one-half pixel (12 bit) at every latch falling and rising edge of the clock Settings for using one pixel per clock DVI Receiver operation mode not programmable - with no I2C involve 24-bit pixel data for one pixel per clock Data enable check for debug issues

35. Implementation VHDL code process(odck_rx) begin case odck_rx is when '0' => data_tx <= qe_rx ( 23 DOWNTO 12); when '1' => data_tx <= qe_rx ( 11 DOWNTO 0); end case; end process; Samples on falling edge Samples on rising edge

36. Documentation generation

37. Questions??? ?