1. 1 Hamming Code Clarissa David Timmy Lau WingChing Lin Jonathan Lee Advisor: Dr. David Parent December 7, 2005

2. 2 Agenda Abstract Introduction –Why a Hamming Code? –Potential Applications –Theory of Operation Calculations Cadence Details Summary of Results Cost Analysis Conclusions

3. 3 Abstract Target Specification –Clock Frequency: 200MHz –Load Capacitance: 30fF –Area: 900x500 micron squared Actual Specification –Clock Frequency: 160MHz –Load Capacitance: 30fF –Area: 932.55 x 915.45 micron squared

4. 4 Introduction Hamming Code –Detects single and double-bit errors Application –Telecommunication (i.e. networking) Theory –Using 4 data bits, can generate 3 correction bits giving a total of 7 bits –Can correct any single bit error

5. 5 Longest Path CELLBIT# WN Load (cm) WP Load (cm) Cg+Cinttphl (s)WN (cm)WP (cm) NAND2A1 3.0000E-142.00E-103.80E-043.38E-04 NAND2B23.80E-043.38E-041.2053E-141.90E-102.22E-041.98E-04 INVA32.22E-041.98E-047.0588E-157.50E-111.53E-042.77E-04 INVB41.53E-042.77E-047.2093E-157.50E-111.55E-042.81E-04 NAND3A51.55E-042.81E-047.3253E-152.30E-103.02E-041.78E-04 INVC63.02E-041.78E-048.0627E-158.00E-111.52E-042.75E-04 INVD71.52E-042.75E-047.1669E-157.50E-111.55E-042.80E-04 NAND2C81.55E-042.80E-047.2926E-151.20E-104.36E-043.92E-04 INVE94.36E-043.92E-041.3902E-149.50E-111.82E-043.28E-04 NAND4A101.82E-043.28E-048.5568E-153.40E-103.15E-041.50E-04 NAND4B113.15E-041.50E-047.8037E-153.40E-103.00E-041.50E-04 INVF123.00E-041.50E-047.5520E-157.50E-111.61E-042.91E-04 NAND2D131.61E-042.91E-047.5893E-151.50E-102.50E-042.24E-04 NAND2E142.50E-042.24E-047.9558E-151.50E-102.50E-042.24E-04 INVG152.50E-042.24E-047.9558E-157.50E-111.67E-043.03E-04 NAND4C161.67E-043.03E-047.9005E-153.40E-102.85E-041.50E-04 NAND3B172.85E-041.50E-047.3002E-152.10E-103.00E-041.78E-04 INVH183.00E-041.78E-048.0177E-157.50E-111.68E-043.05E-04

6. 6 Schematic Gate Level Schematic of Hamming Code Note: This is an Error Generator

7. 7 Schematic Block schematic of Hamming without the flip-flop

8. 8 Schematic Schematic of Hamming Code with flip-flop at the start

9. 9 Layout Layout of Hamming Code

10. 10 Verification: DRC Verification of DRC Passing

11. 11 Verification: LVS Verification of LVS: PASSED!!!!

12. 12 Simulation NCVerilog of Hamming Code Logic

13. 13 Simulation

14. 14 Simulation Simulation of Hamming Code with flip-flop

15. 15 Simulation Simulation of error generator

16. 16 Cost Analysis TaskLength of Time Verifying Logic1 Day Verifying Timing1 Day Layout7 Days Post Extracted Timing1 Day TOTAL TIME10 Days But from us….. FREE!!!!!

17. 17 Lessons Learned EXPOSE YOURSELF TO THE PROJECT EARLY Be organized about your routing Debugging layout Work together as a team EXPOSE YOURSELF TO THE PROJECT EARLY !!!

18. 18 Summary Complete Circuit Clock Frequency: 160MHz Area: 932.55 x 915.45 microns squared Load Capacitance: 30fF

19. 19 Acknowledgements Thanks to Cadence Design Systems Thanks to Professor David Parent Thanks to the current and past students of EE166