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Chap 2.4 - Instruction Representation Jen-Chang Liu, Spring 2006 Adapted from

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1 Chap 2.4 - Instruction Representation Jen-Chang Liu, Spring 2006 Adapted from

2 Review °Instructions: Arithmetic: add, addi, sub Memory access: lw, sw Branch: beq, bne, j comparison: slt, slti, sltu, sltiu

3 Review of Lab#2: memory access.globl str:.asciiz "abcdABCD".text main: … la $s1, str # $s1=str[0] lb $t2, 0($s1) addi $s1, $s1, 1 # $s1=str[1] lb $t2, 0($s1) abcdABCDabcdABCD str str[1] li $t0, 1 # i=1 lb $t2, $t0($s1) # str[i] Wrong!

4 “Computer Organization” I/O systemProcessor Compiler Operating System (Windows 98) Application (programs) Digital Design Circuit Design Instruction Set Architecture Datapath & Control transistors Memory Hardware Software Assembler High level Low level

5 Hierarchy of Programming Languages Low-level High-level Java C Assembly Degree of abstraction operand operation objectsmethod variables arithmetic op. functions registers instruction set machine binary operation code registers

6 Q: How do we represent instructions in machine?

7 Overview °Instructions as Numbers °R-Format °I-Format °Branch instruction: addressing mode °J-Format

8 Instructions as Numbers (1/2) °Currently all data we work with is in words (32-bit blocks): Each register is a word. lw and sw both access memory one word at a time. °So how do we represent instructions? Remember: Computer only understands 1s and 0s, so “ add $t0,$0,$0 ” is meaningless. MIPS wants simplicity: since data is in words, make instructions be words...

9 Instructions as Numbers (2/2) °One word is 32 bits, so divide instruction word into “fields”. °Each field tells computer something about instruction. °We could define different fields for each instruction, but MIPS is based on simplicity, so define 3 basic types of instruction formats: R-format I-format J-format 655565 65516 opcode 6 26

10 Instruction Formats °J-format: used for j and jal °I-format: used for instructions with immediates ( 含常數的指令 ) lw and sw (since the offset counts as an immediate) the branches ( beq and bne ) (but not the shift instructions; later) °R-format: used for all other instructions Registers as operands

11 Overview °Instructions as Numbers °R-Format °I-Format °Branch instruction: addressing mode °J-Format 以暫存器為運算單位的指令

12 R-Format Instructions (1/5) °Define “fields” of the following number of bits each: 655565 opcodersrsrtrtrdrdfunctshamt °For simplicity, each field has a name: °Important: Each field is viewed as a 5- or 6-bit unsigned integer, not as part of a 32-bit integer. Consequence: 5-bit fields can represent any number 0-31, while 6-bit fields can represent any number 0-63. Low-order bits high-order bits 每個 field 看做單獨的數字

13 R-Format Instructions (2/5) °What do these field integer values tell us? opcode : partially specifies what instruction it is (Note: This number is equal to 0 for all R-Format instructions.) funct : combined with opcode, this number exactly specifies the instruction Question: Why aren’t opcode and funct a single 12-bit field? Answer: We’ll answer this later. opcodersrsrtrtrdrdfunctshamt

14 R-Format Instructions (3/5) °More fields: rs (Source Register): generally used to specify register containing first operand rt (Target Register): generally used to specify register containing second operand (note that name is misleading) rd (Destination Register): generally used to specify register which will receive result of computation opcodersrsrtrtrdrdfunctshamt

15 R-Format Example °MIPS Instruction: add $t0,$t1,$t2 => add $8,$9,$10 0910832 ? 000000010010101001000100000? binary representation: decimal representation: opcodersrsrtrtrdrdfunctshamt

16 See p. A-54

17 R-Format Instructions (4/5) °Notes about register fields: Exactly 5 bits => 0~31 => indicate the register number °Final field: shamt : This field contains the amount a shift instruction will shift by. Shifting a 32- bit word by more than 31 is useless, so this field is only 5 bits (so it can represent the numbers 0-31). This field is set to 0 in all but the shift instructions. opcodersrsrtrtrdrdfunct shamt

18 R-Format Example (cont.) °MIPS Instruction: add $t0,$t1,$t2 => add $8,$9,$10 09108320 00000001001010100100010000000000 binary representation: Called a Machine Language Instruction decimal representation: Hex: 0 1 2 a 4 0 2 0 opcodersrsrtrtrdrdfunctshamt

19 Overview °Instructions as Numbers °R-Format °I-Format °Branch instruction: addressing mode °J-Format 以常數為運算單位的指令

20 I-Format Instructions (1/5) °What about instructions with immediates? Ideally, MIPS would have only one instruction format (for simplicity): unfortunately, we need to compromise 5-bit field only represents numbers up to the value 31: immediates may be much larger than this °Define new instruction format that is partially consistent with R-format ! Opcode 6rs 5rt 5rd 5funct 6shamt 5 R-format: c.f. add $t0, $t1, $t2 addi $t0, $t1, 2

21 I-Format Instructions (2/5) °I-format: 65516 opcodersrtimmediate °Again, each field has a name: Compared with R-format: Opcode 6rs 5rt 5rd 5funct 6shamt 5

22 I-Format Instructions (3/5) °What do these fields mean? opcode : same as before except that, since there’s no funct field, opcode uniquely specifies an I-format instruction This also answers question of why R-format has two 6-bit fields to identify instruction instead of a single 12-bit field: in order to be consistent with other formats. Opcode 6rs 5rt 5 Immediate 16 bits Opcode 6rs 5rt 5rd 5funct 6shamt 5 I R

23 I-Format Instructions (4/5) °More fields: rs : specifies the only register operand (if there is one) rt : specifies register which will receive result of computation (this is why it’s called the target register “rt”) opcodersrtimmediate addi $t0, $t1, 1

24 I-Format Instructions (5/5) °The Immediate Field: 16 bits  can be used to represent immediate up to 2 16 different values addi, slti, sltiu : the immediate is sign-extended to 32 bits in real hardware operation lw, sw: immediate = offset -lw $t0, 0($a0) opcodersrtImmediate 16 bits

25 I-Format Example °MIPS Instruction: addi $s5,$s6,-50 => addi $21,$22,-50 82221-50 00100010110101011111111111001110 decimal representation: binary representation: Hex: 2 2 d 5 f f c e opcodersrtimmediate


27 I-Format Problems (1/3) °Problem 1: What if immediates are too big to fit in the immediate field (16 bits only)? -We need a way to deal with a 32-bit immediate in any I-format instruction. How to do this? addi $t0,$t0, 0x2BAB2DCD 16 bits

28 I-Format Problems (2/3) °Solution to Problem 1: Handle it in software (assembler) Don’t change the current instructions: instead, add a new instruction to help out °New instruction: lui register, immediate stands for Load Upper Immediate takes 16-bit immediate and puts these bits in the upper half (high order half) of the specified register sets lower half to 0s 16 reg.

29 I-Format Problems (3/3) °Solution to Problem 1 (continued): So how does lui help us? Example: addi $t0,$t0, 0x2BAB2DCD becomes: lui $a0, 0x2BAB ori $a0, $a0, 0x2DCD add $t0,$t0,$a0 Why not : li $a0, 0x2BAB2DCD

30 How to be an assembler? °Assembly main: bne $t0, $t1, End lui $t3, 0x2BAB ori $t3, $t3, 0x2DCD add $s0, $s1, $t3 End:

31 step 1 °Choose which formats they are? °Write down the formats and how many bits for each field Opcode 6rs 5rt 5rd 5funct 6shamt 5 R-format Opcode 6rs 5rt 5 Immediate 16 I-format

32 step 2 °Write down the encoding of registers

33 Step 3: decide opcode

34 step 4 °Fill the other fields

35 Peer Instruction Which instruction has same representation as 35 ten ? 1. add $0, $0, $0 2. subu $s0,$s0,$s0 3. lw $0, 0($0) 4. addi $0, $0, 35 5. subu $0, $0, $0 6. Trick question! Instructions are not numbers Registers numbers and names: 0: $0,.. 8: $t0, 9:$t1,..15: $t7, 16: $s0, 17: $s1,.. 23: $s7 Opcodes and function fields (if necessary) add : opcode = 0, funct = 32 subu : opcode = 0, funct = 35 addi : opcode = 8 lw : opcode = 35 opcodersrtoffset rdfunctshamt opcodersrt opcodersrtimmediate rdfunctshamt opcodersrt rdfunctshamt opcodersrt

36 Overview °Instructions as Numbers °R-Format °I-Format °Branch instruction: addressing mode °J-Format

37 Branches: PC-Relative Addressing (1/5) °Use I-Format opcodersrtimmediate °opcode specifies beq, bne °rs and rt specify registers to compare °What can immediate specify? Immediate is only 16 bits Label is 32-bit address in memory So immediate cannot specify entire address to branch to.(16 bits 定址空間有限 ) Ex. beq $t0, $t0, Label

38 Branches: PC-Relative Addressing (2/5) °How do we usually use branches? Answer: if-else, while, for Loops are generally small: typically up to 50 instructions ( 迴圈程式段落通常不大 ) Function calls and unconditional jumps are done using jump instructions ( j and jal ), not the branches. °Conclusion: a single branch will generally change the PC by a very small amount.

39 Branches: PC-Relative Addressing (3/5) °Solution: PC-Relative Addressing °16-bit immediate = offset °Now we can branch +/- 2 15 bytes from the PC, which should be enough to cover any loop. … PC Target address: PC + offset offset

40 Branches: PC-Relative Addressing (4/5) °Note: Instructions are words, so they’re word aligned So the number of bytes to add to the PC will always be a multiple of 4.( 指令碼的位址都是四 的倍數 ) So specify the immediate in words. °Now, we can branch +/- 2 15 words from the PC (or +/- 2 17 bytes), so we can handle loops 4 times as large.

41 Branches: PC-Relative Addressing (5/5) °Final Calculation: If we don’t take the branch: PC = PC + 4 If we do take the branch: PC = (PC + 4) + ( immediate * 4) Observations -Immediate field specifies the number of words to jump, which is simply the number of instructions to jump. -Immediate field can be positive or negative. -Due to hardware, add immediate to (PC+4), not to PC; will be clearer why later in course beq(bne) rs, rt, Label

42 Branch Example (1/3) °MIPS Code: Loop:beq $9,$0,End add $8,$8,$10 addi $9,$9,-1 j Loop End: °Branch is I-Format: opcode = 4 (look up in table) rs = 9 (first operand) rt = 0 (second operand) immediate = ???


44 Branch Example (2/3) °MIPS Code: Loop:beq $9,$0,End addi $8,$8,$10 addi $9,$9,-1 j Loop End: °Immediate Field: Number of instructions to add to (or subtract from) the PC, starting at the instruction following the branch. In this case, immediate = 3 *test this in PCspim, set bare machine in the setting PC+4 3 inst.

45 Branch Example (3/3) °MIPS Code: Loop:beq $9,$0,End addi $8,$8,$10 addi $9,$9,-1 j Loop End: 4903 decimal representation: binary representation: 00010001001000000000000000000011

46 Big Idea: Stored-Program Concept °Computers built on 2 key principles: 1) Instructions are represented as numbers. 2) Therefore, entire programs can be stored in memory to be read or written just like numbers (data).

47 Consequence #1: Everything Addressed °Since all instructions and data are stored in memory as numbers, everything has a memory address: instructions, data words both branches and jumps use these °C pointers are just memory addresses °One register keeps address of instruction being executed: “Program Counter” (PC) Basically a pointer to memory: Intel calls it Instruction Address Pointer, which is better

48 Consequence #2: Binary Compatibility °Programs are distributed in binary form Programs bound to specific instruction set Different version for Macintosh and IBM PC °New machines want to run old programs (“binaries”) as well as programs compiled to new instructions

49 Review °Machine Language Instruction: 32 bits representing a single MIPS instruction opcodersrtrdfunctshamt opcodersrtimmediate R I opcodetarget address J °Instructions formats are kept as similar as possible.

50 Jump instruction °J-format °General address: 32 bits 6 bitsTarget:26 bits PC 31… 28 26 bits 00 word alignment

51 J-Format Instructions (1/5) °For branches, we assumed that we won’t want to branch too far, so we can specify change in PC. beq, bne °For general jumps ( j and jal ), we may jump to anywhere in memory. Ideally, we could specify a 32-bit memory address to jump to. Unfortunately, we can’t fit both a 6-bit opcode and a 32-bit address into a single 32-bit word, so we compromise. opcodetarget address J

52 J-Format Instructions (2/5) °Define “fields” of the following number of bits each: 6 bits26 bits opcodetarget address °As usual, each field has a name: °Key Concepts Keep opcode field identical to R-format and I-format for consistency. Combine all other fields to make room for target address.

53 J-Format Instructions (3/5) °For now, we can specify 26 bits of the 32-bit bit address. °Optimization: Note that, just like with branches, jumps will only jump to word aligned addresses, so last two bits are always 00 (in binary). So let’s just take this for granted and not even specify them.

54 J-Format Instructions (4/5) °For now, we can specify 28 bits of the 32-bit address. °Where do we get the other 4 bits? By definition, take the 4 highest order bits from the PC. Technically, this means that we cannot jump to anywhere in memory, but it’s adequate 99.9999…% of the time, since programs aren’t that long. If we absolutely need to specify a 32-bit address, we can always put it in a register and use the jr instruction.

55 J-Format Instructions (5/5) °Summary: New PC = PC[31..28] || target address (26 bits) || 00 Note: II means concatenation 4 bits || 26 bits || 2 bits = 32-bit address PC 31… 28 26 bits 00

56 Addressing mode

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