1. 1 Team M1 Enigma Machine Milestone 7 - 22 March, 2006 Adithya Attawar (M11) Shilpi Chakrabarti (M12) Zavo Gabriel (M13) Mike Sokolsky (M14) Design Manager: Prateek Goenka

2. 2 Status Finished: Behavioral Verilog and C simulation Structural Verilog Logic optimization Module-level spice delay and power simulations Floorplan In Progress: Top-level schematic testing Module layout To do: Global Layout Testing Simulation

3. 3 Design Decisions Optimized layout of smaller gates and modules including muxes, registers, flip flops

4. 4 SRAM pulsing

5. 5 DT FlipFlop

6. 6 SRAM

7. 7 SRAM Results

8. 8 Problems/Questions Top level schematic still not verified This should be taken care of in the next day or two SRAM voltage problems in schematic simulation