1. Team W3: Anthony Marchetta Derek Ritchea David Roderick Adam Stoler Milestone 10: April 5th Chip Level Simulation Overall Project Objective: Design an Air-Fuel Ratio Controller for a small gasoline engine with low emissions and low cost Design Manager: Steven Beigelmacher

3. Status Design Proposal (done) Architecture (done) High Level C Simulation Behavioral Verilog & Test Bench Floorplan & Structural Verilog Gate Level Design (done) Top Level Schematic Verification Component Layout (done) Analog simulation of SRAM and ROM Layout of all components Component Simulation (done) Smaller Multiplier completed Chip-Level Layout (done) Top-level LVS errors Still to be done Full chip Spice Simulations

4. Hallelujah

5. Simulation Plan Cannot run full simulation –Requires ~120 cycles to load SRAM and generate first correct outputs Simulate one iteration of comparisons and index generation for lookup table –Only requires ~10 cycles –Verifies any timing and control issues –Multiplier and SRAM lookup table have already been verified –Still simulate whole chip for accurate loading (many transistors will be inactive)

6. Problems Need to rewire our muxes. Need to add a second clock signal for SRAM to load correctly. These two problems have been fixed in the schematic and simulate correctly.

7. 12bit Input Reg 8X10 SRAM Value Look-up 12bit Input Reg Engine Speed Manifold Pressure 12bit Input Reg Throttle Position Fixed Point Array Multiplier 2:1Mu x 12bit Output Register Control ROM 12bit Input Reg %Oxygen 7X4 SRAM Comparator Look-up 4:1Mux = R0 12bit Register Win Sin[0:1] 2:1Mu x Rcomp Sin[0:1] Index[0:4] Write R1 R2 RowComp[0]RowComp[1] Srow1 Srow2 RowComp[2] 3bit Reg Wcol Index[0:6] Write Rtable 2:1Mu x Scol ColTable[0:3] 2:1Mu x Scol Valid Wmult1 Wmult2 Smult 5bit State Reg Next[0:4] Wout PulseOut[0:11]

8. Top Level Layout 383x273(µm)

9. Layout 383 x 273 (µm) 104,559 (µm2 ) Aspect Ratio: 1.4 Trans. Density:.167 Tran/ µm 2 Transistor Count = 17,465 Clock Speed 1MHz – speed is not our goal

10. Questions????