1. CS 2204 Spring 2006 Experiment 2 Lab 4

2. CS 2204 Spring 2006 Page 2 Xilinx Project Development Steps  Develop the schematic Design the schematic Do integrity tests Test the schematic via functional simulations  Do a Xilinx implementation It maps the components to the CLBs of the chip  Do timing simulations to test the schematic It generates the bit file  Download the bit file to the FPGA It programs the chip

3. Lab 4CS 2204 Spring 2006 Page 3 Developing a digital product  A new chip Which gates & FFs and how many is determined by  Speed, cost, power, etc. goals of the digital product FPGAs are used to test the new chip  Besides the application (major operations) and available components of the technology chosen  A new PCB Which chips and how many is determined by  Speed, cost, power, etc. goals of the digital product  Besides the application (major operations) and available chips of the technology chosen

4. Lab 4CS 2204 Spring 2006 Page 4 Digital circuits consist of gates and FFs  FFs consist of gates Digital circuits consist of gates ! Gates are on chips ! Gates are implemented by electronic components on chips :  Transistors, capacitors, resistors, diodes,…

5. Lab 4CS 2204 Spring 2006 Page 5 Digital circuits consist of gates and FFs  FFs consist of gates Digital circuits consist of gates D FF D FF implementation via gates From ON Semiconductor LS TTL Data Manual

6. Lab 4CS 2204 Spring 2006 Page 6 Gates are on chips ! Electronic components on chips implement gates:  Transistors, capacitors, diodes, resistors,… From ON Semiconductor LS TTL Data Manual 74 LS00 Quad 2-input NAND Gate chip NAND gate implementation via electronic components

7. Lab 4CS 2204 Spring 2006 Page 7 Transistors are the main component and used as switches to implement gates  A switch is open or closed based on the control input value : Open when control is 0 : Closed when control is 1 0 10 1 11

8. Lab 4CS 2204 Spring 2006 Page 8 Implementing AND, OR, NOT gates AND k m k.mk.m AND gate Implemented by two switches k.m k m 1 OR k m k + m OR gate Implemented by two switches k 1 m k + m NOT k k NOT gate (inverter) Implemented by one switch k 1 0

9. Lab 4CS 2204 Spring 2006 Page 9 2-to-1 MUX Implementation AND OR NOT a b a c y(a, b, c) =a.b + a.c y(a, b, c) = a.b + a.c a c a b 1

10. Lab 4CS 2204 Spring 2006 Page 10 Transistors, capacitors, resistors, diodes,… have speed, cost, power, size,.. Properties, determining same features of gates  These properties depend on the technology used : CMOS, BiCMOS, TTL, ECL,… We then need to study substances used for chips Electronic circuits that form the gates A chip Die A chip Transistors and other electronic components are on the die Today, there can be 200 million transistors on a die

11. Lab 4CS 2204 Spring 2006 Page 11 Semiconductor substances and circuits Our FPGA chip is CMOS Most microprocessors are CMOS

12. Lab 4CS 2204 Spring 2006 Page 12 Why are chips cheap today ? Chips use semiconductors today  Silicon is the most common semiconductor to implement electronic components sea sand is the source  Other substances : Silicon Germanium, Gallium Arsenide  More expensive but faster technologies Niobium  Superconducting : the fastest.  Not a semiconductor

13. Lab 4CS 2204 Spring 2006 Page 13 Gate Features  Determined by switch features Speed  Gate delay, t p, propagation delay : the time it takes for the gate output to change after an input is changed a b y a b y tptp

14. Lab 4CS 2204 Spring 2006 Page 14 Gate delays result in glitches AND OR NOT a b a c y ab ac Glitch (timing hazard) a Do not use the output during this time 1 1 10 11 110 y ac a ab

15. Lab 4CS 2204 Spring 2006 Page 15 Gate Features  Cost : determined by the substance, family, the number of inputs, etc.  Power consumption : amount of electrical power consumed in Watts Determined by the substance, family, the number of inputs, etc. Indirectly determines the density of the chip

16. Lab 4CS 2204 Spring 2006 Page 16 Gate Features  Size : determined by the substance, family, the number of inputs, the transistor circuit  Fan-in : the number of inputs the gate has a by c The fan-in is three

17. Lab 4CS 2204 Spring 2006 Page 17 Gate Features  Fan-out : the number of gate inputs that can be connected to a gate output Determined by substance, family, the transistor circuit, etc. If the fan-out is exceeded the output can be damaged or its value may not be electrically “strong” to be interpreted as 1 or 0

18. Lab 4CS 2204 Spring 2006 Page 18 Gate Features  In order to increase the fan-out buffers are used Regular buffers (not input nor output buffers) are used to increase the fan-out  A buffer is an electronic circuit that is used to electrically “drive” large currents, hence many inputs It can also have circuits to filter noise and strengthen the signal

19. Lab 4CS 2204 Spring 2006 Page 19 Gate Features  Increasing the fan-out a b y c..... Use a buffer ! But, the input to output delay is increased

20. Lab 4CS 2204 Spring 2006 Page 20 Digital Engineering Terminology a b a c U1 U2 U3 U2 has no Load U2 output is not used y U4 Multiple drivers on output y U3 and U4 outputs are short circuited U4 input has no driver U4 input is not connected to an output. Its input value is Hi-Z (High-Impedance) as there is infinite impedance (resistance) into the U4 input so no current can flow in

21. Lab 4CS 2204 Spring 2006 Page 21 Silicon Technology Today Our FPGA chip is CMOS Most microprocessors are CMOS

22. Lab 4CS 2204 Spring 2006 Page 22 Semiconductor Technology Today  Moore’s Law holds since the 1960s : Every two years the number of transistors on a chip doubles  Every two years density of memory chips doubles  Due to Moore’s law and other reasons : Every two years the speed of microprocessors doubles

23. Lab 4CS 2204 Spring 2006 Page 23 Silicon Technology Today Multi-chip module (MCM, >1 die on chip) ? Giga Scale ? Multi-chip module (MCM, >1 die on chip) ? Giga Scale ? IBM 8-core Cell Processor with 234M transistors at 4GHz calculating 256B floating-point operations a second Today

24. Lab 4CS 2204 Spring 2006 Page 24 Power Density Increasing Exponentially! Watts/cm 2 1 10 100 1000  i386 i486 Pentium® Pentium® Pro Pentium® II Pentium® III Hot plate RocketNozzleRocketNozzle Nuclear Reactor Courtesy : “New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies” – Fred Pollack, Intel Corp. Micro32 conference key note - 1999. Courtesy Avi Mendelson, Intel. Pentium® 4 Power doubles every 4 years

25. Lab 4CS 2204 Spring 2006 Page 25 Switch evolution 1)Electromechanical : relays 2)Electronic Vacuum tubes Discrete transistors Integrated circuit transistors  SSI transistor  MSI transistor  LSI transistor  VLSI transistor  ULSI transistor  MCM transistor ? Giga Scale transistor ?

26. Lab 4CS 2204 Spring 2006 Page 26 Switch evolution 3)Optical switches ? 4)Molecular switches ?  Biological ? 5)????

27. Lab 4CS 2204 Spring 2006 Page 27 Long Term Forecast  SEMATECH : consortium of semiconductor manufacturers from America, Asia and Europe.  SEMATECH predictions for year 2020 (from its updated 2004 International Technology Roadmap for Semiconductors, ITRS, study) : Clock speed : 73 GHz Number of transistors on a microprocessor chip : 17 Billion 256Gbit DRAM chips  http://www.sematech.org

28. Lab 4CS 2204 Spring 2006 Page 28 Today’s Xilinx Work  We will not develop a Xilinx project  We will study (analyze) the term project and modify portions of ppm schematics to learn more about The Xilinx software Study the Digilent board and the FPGA chip

29. Lab 4CS 2204 Spring 2006 Page 29 Today’s Xilinx Lab Work 1.Download the Experiment 2 project, exp2, from the course web site to the CS2204 folder 2.Extract (unzip) exp2 in the same folder The exp2 folder will be created for the project

30. Lab 4CS 2204 Spring 2006 Page 30 Today’s Xilinx Lab Work 3.Start the Xilinx Foundation software and open the exp2 project in the exp2 folder 4.Study schematics 4 and 6  Enter the team information to all schematics  Study the 4-bit 2-to-1 MUX labeled U109  Do a Hierarchy Push to see the implementation of the 4-bit 2-to-1 MUX by Xilinx  Confirm it consists of 4 (1-bit) 2-to-1 MUXes  Delete this MUX so it can be implemented on schematic 6 by using separate 4 2-to-1 MUXes  Study the (1-bit) 2-to-1 MUX on schematic 6  Label the wires so this MUX implements one of the four MUXes of component 109

31. Lab 4CS 2204 Spring 2006 Page 31 Today’s Xilinx Lab Work  Separate the output wire form its gate and do an integrity test of this schematic sheet to see the warning on the project manager window  Copy and paste this MUX and then label the wires to implement the seocnd MUX of the 4-bit 2-to-1 MUX  Repeat the above step one more time  Draw the last 2-to-1 MUX yourself and label its wires  Do an integrity test of this schematic sheet to see if there are problems  Do a Xilinx IMPLEMENTATION and make sure there are no errors

32. Lab 4CS 2204 Spring 2006 Page 32 Today’s Xilinx Lab Work  Take a look at the FPGA CLB usage by using the FPGA Editor  Play the ppm game to complete the testing of our design  Note that we did not do functional and timing simulations step to test our circuit  We should have done them !  But, to simplify our learning today, we skipped them today

33. Lab 4CS 2204 Spring 2006 Page 33 Today’s Xilinx Lab Work 5.Download the Ppm human vs. human project, ppmhvsh, from the course web site to the CS2204 folder 6.Extract (unzip) ppmhvsh in the same folder The ppmhvsh folder will be created for the project 7.Open the ppmhvsh project in the ppmhvsh folder 8.Study the schematics

34. Lab 4CS 2204 Spring 2006 Page 34 Today’s Xilinx Lab Work 7.Do a Xilinx IMPLEMENTATION 8.Check the Implementation Log file to see the number of warnings and the CLB utilization 9.Download the bit file and play the game with your partner

35. Lab 4CS 2204 Spring 2006 Page 35 Today’s Xilinx Lab Work will cover the following Xilinx actions and concepts  Placing team info on schematics  Integrity tests  Searching for components on the Xilinx component library  Copying and pasting schematics via ctrl-c and ctrl-v  The Select and Drag mode

36. Lab 4CS 2204 Spring 2006 Page 36 Today’s Xilinx Lab Work will cover the following Xilinx actions and concepts  Labeling wires and components Wire names follow application and block partitioning naming requirements  Except for wires that are connected IBUFs, OBUFs, IPADs and OPADs Component names start with a U  Except if it is a BUF, IBUF, OBUF, IPAD or OPAD  Xilinx IMPLEMENTATONs Observing the actual CLB and pad utilization through the FPGA editor

37. Lab 4CS 2204 Spring 2006 Page 37 QUESTIONS ?