Presentation is loading. Please wait.

Presentation is loading. Please wait.

1 Multi-Rate Digital Signal Processing Y. C. Jenq, Ph.D. Department of Electrical & Computer Engineering Portland State University Portland, Oregon 97207.

Similar presentations


Presentation on theme: "1 Multi-Rate Digital Signal Processing Y. C. Jenq, Ph.D. Department of Electrical & Computer Engineering Portland State University Portland, Oregon 97207."— Presentation transcript:

1 1 Multi-Rate Digital Signal Processing Y. C. Jenq, Ph.D. Department of Electrical & Computer Engineering Portland State University Portland, Oregon 97207 jenq@ece.pdx.edu

2 2 Decimation System (Down Sampling) M x d [n]x[n] M=3

3 3 x d [n] = x[nM],where M is an integer X d (z) =  n x d [n]z -n =(1/M)  m=0,(M-1) X(z (1/M) e -jm2  /M ) X d ( e j  ) =(1/M)  m=0,(M-1) X(e j(  -m2  /M ) Decimation System (Down Sampling)

4 4 0  0 22 M=3 0  X(e j  )X(e j  ) X(e j(  ) X(e j(  ) X d (e j  ) =(1/M)  m=0,(M-1) X(e j(  -m2  /M ) 44 22

5 5 Sampling Rate Reduction System M y d [n] x[n] Low-pass filter with cutoff at  /M y[n]

6 6 Interpolation System (Up Sampling) L x u [n]x[n] L=3

7 7 Interpolation System (Up Sampling) x u [n] = x[n/L],n = 0, ±L, ±2L, … 0,otherwise X u (z) =  n x u [n]z -n = X(z L ) X u ( e j  ) = X(e j  L )

8 8 Interpolation System (Up Sampling) 0 2  L=3 X(e j  L )X(e j  ) X u ( e j  ) = X(e j  L )

9 9 L Sampling Rate Increase System y[n] x[n] Low-pass filter with cutoff at  /L x u [n]

10 10 Decimation and Interpolation x[n] M M y[n] M=3

11 11 Decimation and Interpolation x[n] M M LetW M = e -j2  /M Y(z)= (1/M)  m=0,(M-1) X(ze -jm2  /M ) = (1/M)  m=0,(M-1) X(zW M m ) Y(e j  )= (1/M)  m=0,(M-1) X(e j(  -m2  /M) ) y[n]

12 12 Decimation and Interpolation Y(e j  )= (1/M)  m=0,(M-1) X(e j(  -jm2  /M) ) 0 0 2    M=3 0 X(e j  ) X(e j(  ) X(e j(  ) 2 

13 13 Fractional Sampling Rate Change L y[n] x[n] Low-pass filter with cutoff at min(  /L,  /M) M

14 14 Block Interconnection Identities M C M C  M M M  Multiply by a Constant

15 15 Block Interconnection Identities M M M 

16 16 LC LC  L L L  Block Interconnection Identities

17 17 Block Interconnection Identities L L L 

18 18 Multi-Rate Identities M H(z M ) M  H(z) LH(z L ) L  H(z)

19 19 Multi-rate Switch Models 3 3 3    n = 0, 3, 6,… n = -1, 2, 5,… n = -2, 1, 4,… x[n]

20 20 Multi-rate Switch Models 3 3 3   x[n]  x[3n] x[3n-1] x[3n-2] Serial to Parallel Converter x[n]

21 21 Multi-rate Switch Models  n = 2, 5, 8,… n = 1, 4, 7,… n = 0, 3, 6,… 3 3 3   x 1 [n] x 2 [n] x 3 [n]

22 22 Multi-rate Switch Models 3 3 3    x 1 [n] x 2 [n] x 3 [n] x[3n+2] x[3n+1] x[3n] Parallel to Serial Converter x[n]

23 23 Poly-phase Structure of Decimation Filter 3   x[n] D 0 (z 3 ) D 2 (z 3 ) D 1 (z 3 ) H(z) = D 0 (z 3 )+ z -1 D 1 (z 3 )+z -2 D 2 (z 3 ) y[n] y[3n] H(z) 3 x[n] y[3n] y[n]

24 24 3 3 Poly-phase Structure of Decimation Filter   x[n] D 0 (z 3 ) D 2 (z 3 ) D 1 (z 3 ) 3 y[3n] H(z) = D 0 (z 3 )+ z -1 D 1 (z 3 )+z -2 D 2 (z 3 )

25 25 3 3   x[n] D 0 (z) D 2 (z) D 1 (z) 3 y[3n] Poly-phase Structure of Decimation Filter H(z) = D 0 (z 3 )+ z -1 D 1 (z 3 )+z -2 D 2 (z 3 )

26 26 x[3n] x[3n-1] x[3n-2] Serial to Parallel Converter x[n] Poly-phase Structure of Decimation Filter D 0 (z) D 2 (z) D 1 (z) y[3n] H(z) = D 0 (z 3 )+ z -1 D 1 (z 3 )+z -2 D 2 (z 3 )

27 27 Poly-phase Structure of Interpolation Filter 3     x[n] H(z) = z -2 I 0 (z 3 )+ z -1 I 1 (z 3 )+I 2 (z 3 ) y[n] I 0 (z 3 ) I 2 (z 3 ) I 1 (z 3 ) H(z) 3 x[n] y[n]

28 28 Poly-phase Structure of Interpolation Filter 3 x[n] H(z) = z -2 I 0 (z 3 )+ z -1 I 1 (z 3 )+I 2 (z 3 ) y[n] I 0 (z 3 ) I 2 (z 3 ) I 1 (z 3 ) 3 3  

29 29 Poly-phase Structure of Interpolation Filter 3 x[n] H(z) = z -2 I 0 (z 3 )+ z -1 I 1 (z 3 )+I 2 (z 3 ) I 0 (z) I 2 (z) I 1 (z) 3 3 y[n]  

30 30 Poly-phase Structure of Interpolation Filter x[n] H(z) = z -2 I 0 (z 3 )+ z -1 I 1 (z 3 )+I 2 (z 3 ) I 0 (z) I 2 (z) I 1 (z) y[3n+2] y[3n+1] y[3n] Parallel to Serial Converter y[n]

31 31 Poly-phase Structure of Fractional Sampling Rate Filter 3     x[n] F 0 (z 3 ) F 2 (z 3 ) F 1 (z 3 ) 4 y[n] H(z) = z -2 F 0 (z 3 )+ z -1 F 1 (z 3 )+F 2 (z 3 ) (M=4, L=3)

32 32 Poly-phase Structure of Fractional Sampling Rate Filter (M=4, L=3) 3     x[n] F 0 (z) F 2 (z) F 1 (z) 4 y[n] 3 3 H(z) = z -2 F 0 (z 3 )+ z -1 F 1 (z 3 )+F 2 (z 3 )

33 33 Poly-phase Structure of Fractional Sampling Rate Filter (M=4, L=3) 3   x[n] F 0 (z) F 2 (z) F 1 (z) 4 y[n] 3 3 H(z) = z -2 F 0 (z 3 )+ z -1 F 1 (z 3 )+F 2 (z 3 )    

34 34 Poly-phase Structure of Fractional Sampling Rate Filter (M=4, L=3) 3   x[n] F 0 (z) F 2 (z) F 1 (z) y[n] 3 3 H(z) = z -2 F 0 (z 3 )+ z -1 F 1 (z 3 )+F 2 (z 3 )     4 4 4

35 35 Poly-phase Structure of Fractional Sampling Rate Filter (M=4, L=3) 3   x[n] F 0 (z) F 2 (z) F 1 (z) y[n] 3 3 H(z) = z -2 F 0 (z 3 )+ z -1 F 1 (z 3 )+F 2 (z 3 )     4 4 4

36 36 Poly-phase Structure of Fractional Sampling Rate Filter (M=4, L=3) 3   x[n] F 0 (z) F 2 (z) F 1 (z) y[n] 3 3 H(z) = z -2 F 0 (z 3 )+ z -1 F 1 (z 3 )+F 2 (z 3 )     4 4 4

37 37 Poly-phase Structure of Fractional Sampling Rate Filter (M=4, L=3)   x[n]F 0 (z) F 2 (z) F 1 (z) y[n] H(z) = z -2 F 0 (z 3 )+ z -1 F 1 (z 3 )+F 2 (z 3 ) 4 4 4 Parallel to Serial Converter

38 38 Poly-phase Structure of Fractional Sampling Rate Filter (M=4, L=3)   x[n]F 0 (z) F 2 (z) F 1 (z) y[n] H(z) = z -2 F 0 (z 3 )+ z -1 F 1 (z 3 )+F 2 (z 3 ) F k (z) = F k0 (z 4 )+ z -1 F k1 (z 4 )+z -2 F k2 (z 4 )+z -3 F k3 (z 4 ) 4 4 4 Parallel to Serial Converter

39 39 Poly-phase Structure of Fractional Sampling Rate Filter (M=4, L=3)   x[n] F 2 (z) F 1 (z) y[n] H(z) = z -2 F 0 (z 3 )+ z -1 F 1 (z 3 )+F 2 (z 3 ) F k (z) = F k0 (z 4 )+ z -1 F k1 (z 4 )+z -2 F k2 (z 4 )+z -3 F k3 (z 4 ) 4 4 Parallel to Serial Converter Serial to Parallel Converter F k0 F k1 F k2 F k3

40 40 Poly-phase Structure of Fractional Sampling Rate Filter (M=4, L=3)    x[n] F 2 (z) F 1 (z) y[n] H(z) = z -2 F 0 (z 3 )+ z -1 F 1 (z 3 )+F 2 (z 3 ) F k (z) = F k0 (z 4 )+ z -1 F k1 (z 4 )+z -2 F k2 (z 4 )+z -3 F k3 (z 4 ) 4 4 Parallel to Serial Converter Serial to Parallel Converter F k0 F k1 F k2 F k3  

41 41 Efficient Design for Very Narrow-band Filters G(z M ) x[n] y[n]H(z) x[n]y[n]F(z)

42 42 Efficient Design for Very Narrow-band Filters G(z M ) H(z) F(z) 0  G(z) 0  0  0   p  s pp  s ss pp ss  Desired passband Images pp

43 43 Efficient Design for Very Narrow-band Filters G(z M ) x[n]y[n]F(z) M G(z ) x[n]y[n]F(z) M G(z ) x[n] y[n] F 0 (z ) M z -1 M F 1 (z ) +

44 44 Efficient Design for Very Narrow-band Filters G(z ) x[n] y[n] F 0 (z ) F 1 (z ) + Serial to Parallel Converter F M-1 (z )

45 45 Multi-stage Decimation System H(z ) x[n]y[n] M G(z ) x[n] y[n] F(z) M 1 G(z M 1 ) x[n]y[n]F(z) M 1 M 2 M 2

46 46 Multi-stage Decimation System x[n] y[n] F 0 (z ) F 1 (z ) + Serial to Parallel Converter F M 1 -1 (z ) G 0 (z ) G 1 (z ) + Serial to Parallel Converter G M 2 -1 (z )

47 47 Multi-stage Interpolation System H(z ) x[n]y[n] L G(z ) x[n] y[n] F(z) L 1 G(z L 1 ) x[n]y[n]F(z) L 1 L 2 L 2

48 48 Multi-stage Interpolation System x[n] y[n] F 0 (z ) F 1 (z ) F L 1 -1 (z ) G 0 (z ) G 1 (z ) Parallel to Serial Converter G L 2 -1 (z ) Parallel to Serial Converter


Download ppt "1 Multi-Rate Digital Signal Processing Y. C. Jenq, Ph.D. Department of Electrical & Computer Engineering Portland State University Portland, Oregon 97207."

Similar presentations


Ads by Google