1. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Multirate Processing of Digital Signals: Fundamentals VLSI Signal Processing 台灣大學電機系 吳安宇

2. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Outline Introduction Sampling Rate Conversion Multistage Implementation Practice Structure Polyphase Implementation

3. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Motivation Definition More than one sampling rate (clock) are used in a system Module 1Module 2 clock 1 clock 2 ?

4. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Conversion Approach Analog approach Digital approach (multirate DSP system)

5. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Analog Approach Advantages Simple Straightforward Arbitrary sampling rate Disadvantages D/A & A/D converter are needed Ideal (near perfect) lowpass filter is needed Introduced noise and distortion

6. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Digital Approach Sampling rate conversion Interpolation Increase the sampling rate Decimation Decrease the sampling rate

7. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Sampling Theory If the highest frequency component in a signal is f max, then the signal should be sampled at the rate of at least 2f max for the samples to describe the signal completely, i.e., For Fs < 2fmax, alias occurs in the sampling process.  Alias Distortion (aliasing)

8. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Aliasing f max FsFs f -F s X(f)

9. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Interpolation by L LL h(m)h(m)

10. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Interpolation by L LL h(m)h(m)

11. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Decimation by M h(m)h(m) MM

12. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU h(m)h(m) MM Decimation by M

13. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Conversion by a Rational Factor M/L Cascade of two process LL h1(m)h1(m)h2(m)h2(m) MM Interpolation by LDecimation by M

14. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Conversion by a Rational Factor M/L A more efficiency implementation LL h (m)h (m) MM

15. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Multistage Implementation LL h(m)h(m) L1L1 h(m)h(m) L2L2 LILI L1L1 h1(m)h1(m) L2L2 h2(m)h2(m) L1L1 h1(m)h1(m)

16. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Multistage Implementation Advantages Reduce the complexity Reduce storage devices (registers) Simplify (relax) filter design problem Reduce the finite wordlength effect Disadvantages Increase the control circuit Difficulty in choosing I and best Lj for 1  i  I

17. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Interpolated FIR (IFIR) Approach Nothing to do with interpolation and decimation Conceptually similar Suitable for narrowband FIR filter design LPF HPF BPF

18. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Desired narrowband response Assume required filter order is N. Stretched filter Required filter order is reduced to N/2. Interpolated version of stretched filter Required filter order is still N/2. DesiredUndesired Image suppresser Required filter order is M. Order (N/2+M) is needed to implement! (N/2+M) << N for small M Application: Interpolated FIR (IFIR)

19. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Interpolated FIR (IFIR) (a) G(z)(a) G(z 2 ) (a) G(z 2 )I(z)(b) I(z)

20. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Interpolated FIR (IFIR) Quantity Compared Filter order Number of Multipliers Number of Adders Conventional Method 233 117 233 IFIR Method 131 66 131 G(z)I(z)Total 6 4 6 268 70 137

21. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Some Useful Operations Duality and Transposition A dual system is that performs a complementary operation to that of an original system, and it can be constructed form the original system through the process of transposition. The transposition operation is one in which the direction of all branches in the network are reversed, and the roles of the input and output of the network are interchanged.

22. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Duality and Transposition transposition z -1

23. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU LL Duality and Transposition They are not true in time-varying system, but can be treated as sampling rate reverse process. LL  M M  M M  M M h(n)h(n)  M M h(n)h(n)  M M h(n)h(n) LL  M M h(n)h(n)  L L transposition

24. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Practical Structure Decimation  M M h(n)h(n) z -1  M M  M M  M M  M M  M M  M M  M M  M M  M M

25. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Practical Structure Interpolation LL h(n)h(n) z -1 LL LL LL LL LL LL

26. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Application: Polyphase FIR Filter Polyphase decomposition h(n)h(n) z -1 E0(zM)E0(zM) E1(zM)E1(zM) E M-1 (z M )

27. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Polyphase FIR Filter Noble identity E (zM)E (zM) MM E (z)E (z) MM E (z)E (z) LL E (zM)E (zM) LL

28. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Polyphase FIR Filter H (z)H (z) 33 z -1 33 h0h0 h1h1 h2h2 h3h3 h4h4 h5h5 h0h0 z -3 33 h3h3 h1h1 h4h4 h2h2 h5h5 z -1 33 E0(z3)E0(z3) E1(z3)E1(z3) E2(z3)E2(z3)

29. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Polyphase FIR Filter z -1 E0(z3)E0(z3) E1(z3)E1(z3) E2(z3)E2(z3) 33 33 33 h0h0 z -3 h3h3 h1h1 h4h4 h2h2 h5h5 z -1 33 33 33 E0(z)E0(z) E1(z)E1(z) E2(z)E2(z) 33 33 33 33 33 33 h0h0 h3h3 h1h1 h4h4 h2h2 h5h5

30. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Structure Comparison z -1 33 33 33 h0h0 h3h3 h1h1 h4h4 h2h2 h5h5 33 33 33 33 33 33 h0h0 h1h1 h2h2 h3h3 h4h4 h5h5 Direct implementation Polyphase implementation