1. Design of a Power-Efficient Interleaved CIC Architecture for Software Defined Radio Receivers By J.Luis Tecpanecatl-Xihuitl, Ruth Aguilar-Ponce, Ashok Kumar, Magdy A. Bayoumi Center for Advanced Computer Studies (CACS) University of Louisiana at Lafayette Lafayette, LA, USA

2. 2 Outline Introduction Goal Cascaded-Integrator-Comb (CIC) Filter Proposed Architecture Results Conclusions

3. 3 Introduction Two important current factors targeting Circuits for Communications: –High Data Rates –Multistandard Devices * Topics in Circuits for Communications IEEE Communications Magazine, August 2005

4. 4 Introduction –High Data Rates Much information in is being to transferred between many of these devices PVR to flat- screen may require 221-1327 Mb/s. Downloading 1000 songs from a media center or Pc to MP3 player require 200 Mb/s in a reasonable amount of time. * Topics in Circuits for Communications IEEE Communications Magazine, August 2005

5. 5 –Multistandard Devices Portable devices integrating not only camera and cellphone, but also WLAN. Personal Video Recorder (PVR), Gaming and Digital TV. At the same time dissipating low power for long battery lifetime.

6. 6 Introduction Use of Multi-Standard Digital Receiver Transition between generations –2G  3G  4G 4G “ABC” Always Be Connected –Data Networks, PCS, Bluetooth, and more

7. 7 Introduction Old Standard s Data Nets Next Generation PCS Nets 3G 2G 4G Specific Standard

8. 8 Introduction Several Communication Standards Incompatibility between them –For Example GSM in USA vs. Europe Many devices per user High Cost of new infrastructure

9. 9 Introduction Benefits of Multi-Standard Device –Several Standards –Take advantage of current infrastructure –Take advantage of different service providers –Configurable by a PC, same provider or by itself

10. 10 Introduction How can this be possible? –Software-defined Radio Implement the different functionalities of a transceiver by means of software Flexibility AnalogDigital Anti-aliasing Filter ADC LNA DSP

11. 11 Introduction Architecture –Going so close to the antenna Analog Digital Anti-aliasing Filter ADC LNA H(z) RR RR Multistage Decimation Filters I Q NCO

12. 12 Introduction Digital Down Converter –Analog-to-Digital Converter (ADC) –Numerical Control Oscillator (NCO) –Mixers (Multipliers) –Decimator Filter Frequency translation Computational intensive Power demanding

13. 13 Introduction Accelerator –Dedicated pieces of hardware which are not programmable –Low power consumption –Reduced Area –Flexibility ADCDAC DSP accelerators

14. 14 Introduction –Decimator Digital Filter Downsampler H(z) MM F in F out = F in /M  22  X(e j  )  0  22  H(e j  )   /M 1 0   W(e j  )   /M 0  Y(e j  ’ )   /M 0 2  /M4  /M 6  /M 8  /M ’’  0 22 44 66 88 If M >> 2 then Coefficient length of H(z) Increase CIC good candidate

15. 15 Introduction Distribution of power consumption on a Tap (multiplication, addition) –Multiplication: 40% to 76% of total power consumption on each tap –Additions: 14% to 25% of total power consumption on each tap Tap Filter  Multiplication, Addition and Delay

16. 16 Major sources of power dissipation in digital CMOS circuits –Switching –Short-circuit –Leakage currents P total = p t (C L  V  V dd  f clk ) + I sc  V dd + I leakage  V dd

17. 17 Introduction Process Design –Identification of the blocks or parts consuming an important fraction of the power during optimization process. 2.-Algorithm 3.-Architecture 4.-Logic/Circuit 5.-Device/Process 1.-System

18. 18 Goal 1.Power Reduction on CIC Filter –Reduced frequency of operation –Voltage Scaling 2.One structure to filter both Signals –Interleaving 3.Common Structure for different communication standards

19. 19 CIC Filter Cascaded Integrator- Comb Filter Advantages –Multiplierless implementation –No memory storage Integrator MM Comb fsfs f s /M MM z -1 k stages Wide wordlength 39 bits19 bits

20. 20 CIC Filter Two CIC filters –Double area –Power consumption –Integrator Section Frequency input Wide Wordlength Q CIC Multistage Filters ADC Q I I Integrator MM Comb fsfs f s /M

21. 21 Proposed Architecture Polyphase filter operates at frequency f/R 1, where f is the input frequency. The polyphase filter structure for decimation filtering helps to reduce the speed requirement grouping the filter in subfilters. The serial input is passed to be filter by the subfilters. The outputs are added to obtain the final output. Thus, the subfilters will operate at reduced frequency fs/D, where D is the factor of decimation

22. 22 Proposed Architecture The dynamic power dissipation in digital CMOS circuits can be modeled as The polyphase architecture is composed of polyphase components operating at the rate of f/M. Therefore, in these polyphase components, it is possible to reduce the voltage supply, which has an important impact on the power consumption. V’ dd can be approximated by

23. 23 Proposed Architecture Voltage Scaling –The obtained scaled voltage supply causes no degradation in the performance of the whole structure. For the stages after the polyphase CIC filter the same voltage supply scaled is used without no decrement effect on performance because the sampling rate is reduce each time. StandardDecompositionV’ dd # Adders Mobitex  5  107 1.48 V7 Ardis  5  107 1.48 V7 GSM  8 1.27 V18 IS-95 55 1.48 V7 UMTS 55 1.48 V7

24. 24 Results Wordlengths on CIC filter StandardSample Rates First decimation factor Wordlength CIC – 3 stages [1] Mobitex 85.6 MHz  20 KHz  535 36 bits – 27bits – 19bits 16bits - 15bits – 14 bits Ardis 85.6 MHz  48 KHz  535 36 bits – 27bits – 19bits 16bits - 15bits – 14 bits GSM 80 MHz  541.6 KHz  64 28 bits – 23bits – 18bits 16bits – 15bits – 14bits IS-95 80 MHz  2.4576 MHz 55 17bits – 17bits – 16bits 16bits – 15bits – 14bits UMTS 80 MHz  7.68 MHz 55 17bits – 17bits – 16bits 16bits – 15bits – 14bits

25. 25 Results Power estimation –Three different factors –For our estimation, adders are the major power consumer blocks for the direct CIC filter in the new architecture due to their dominant capacitance

26. 26 Results where P 0 denoted the power consumption of the reference system. The previous estimations correspond to the three different decompositions showed in previous Table. Therefore, the power consumption of the Interleaved CIC polyphase architecture is only around 15% of the original system.

27. 27 Results Frequency Response –Interleaved CIC polyphase structure is simulated in MATLAB

28. 28 Conclusions Combination of different methods has been adopted to reduce the power consumption on CIC filters used on multistandard digital receivers implemented as software defined radio. Interleaving both signals I and Q, in a polyphase architecture results in a more efficient structure which works at low frequency.

29. 29 Conclusions On each polyphase component the voltage supply is scaled to reduce the power consumption without compromising the performance of the whole architecture. The power consumption in the proposed architecture is estimated to be approximately 15% of the common architecture on the three cases.

30. Questions Suggestions or Comments