1. Rasit Onur Topaloglu and Alex Orailoglu {rtopalog | alex}@cse.ucsd.edu University of California at San Diego Computer Science and Engineering Department La Jolla, CA, 92093, USA On Mismatch in the Deep Sub-Micron Era: from Physics to Circuits

2. Outline -A Brief Overview of Mismatch -Challenges -Design Flow Impact -Estimation of High Level Parameters -Random Variation Effects -Accurate Mismatch Modeling -Previous Work -Contributions -Mismatch Prediction Techniques -Incorporation to Design Flow -Experimental Verification -Insights for Future Modeling -Conclusions

3. A Brief Overview of Mismatch Mismatch = the difference of parameters in matched transistors I ref V b1 V b2 V b3 60 300 60 120 60 30 1:1 = Δ( global + local + random transistor parameter variations) Proper circuit operation requires high precision matching for certain transistors 1:2

4. Impact of Mismatch on VLSI Design -Mismatch caused soft errors (reduction in gain, higher output R) -Critical mismatch necessitates re-design Yield loss Increased time to market * Design for mismatch * Estimate effects of mismatch during design to reduce iterations

5. -keeping standard analog design flow intact -early handling of mismatch -estimating effects of mismatch on high level circuit parameters -correlation-sensitive methods -propagation of mismatch effects between circuit blocks Traditional Challenges DSM Challenges -consideration of random effects -accurate mismatch modeling

6. Analog Design Flow Manual design SPICE simulations Select architecture and technology Optimizations Test & diagnosis after production Behavioral level design and simulations Costly redesign needed due to late observation of mismatch effects SPICE simulations Optimizations

7. Analog Design Flow Manual design SPICE simulations Select architecture and technology Optimizations Test & diagnosis after production Behavioral level design and simulations Essential to help emulate experienced designers so as to accomplish heavy reduction in iterations by early exploration Costly redesign needed due to late observation of mismatch effects Manual design

8. -keeping standard analog design flow intact -early handling of mismatch -estimating effects of mismatch on high level circuit parameters -correlation-sensitive methods -propagation of mismatch effects between circuit blocks Current Challenges DSM Challenges -consideration of random effects -accurate mismatch modeling

9. Propagation of Mismatch I ref Current mirror 99 % falls in this range actual pdf *Worst-case propagation between blocks causes unrealistic accumulation of errors *Designing while considering such large variations impossible in DSM *Correlations between parameters accentuate this error Bandgap reference circuit I ref

10. -keeping standard analog design flow intact -early handling of mismatch -estimating effects of mismatch on high level circuit parameters -correlation-sensitive methods -propagation of mismatch effects between circuit blocks Current Challenges DSM Challenges -consideration of random effects -accurate mismatch modeling

11. Fabrication accuracy cannot keep up with feature size shrinkage rate, as: *Random effects do not scale proportional to parameter scaling Wafer radius t ox (x40nm) Wafer radius t ox (x4nm) newer technology The Increasing Importance of Random Effects *Mismatch groups closer than ever before, therefore: REs assume increased importance compared to previous technology PVE RE

12. Fabrication accuracy cannot keep up with feature size shrinkage rate, as: *Errors occurring from diffusion cause PV distributions that have similar    across different technologies Wafer radius t ox (x40nm) Wafer radius t ox (x4nm) newer technology The Increasing Importance of Random Effects *Mismatch groups closer than ever before, therefore: REs assume increased importance compared to previous technology PVE

13. -keeping standard analog design flow intact -early handling of mismatch -estimating effects of mismatch on high level circuit parameters -correlation-sensitive methods -propagation of mismatch effects between circuit blocks Current Challenges DSM Challenges -consideration of random effects -accurate mismatch modeling

14. Modeling Mismatch Sources I ref V b2 V b1 60 300 60 120 60 30 300+2+1300+2+-2 300 303 *Process variations w/o mismatch tend to effect linearly; mismatch effects non-linearly *Similar reasoning applies to other physical parameters of matched transistors GOAL: predict effects of mismatch on high level circuit parameters PVE and mismatch effects on circuit gain: W M1 W M2 G Nominal : 300 300 100 PVE+RE w/o mismatch: 303 303 102 297 297 98 PVE+RE with mismatch: 303 300 99 297 300 90 PVE REPVE RE

15. Modeling Mismatch Sources NV1 + PVE1 + RE1 NV1 NV2 + PVE2 + RE2 NV2. MR  physical parameters * MR = 1 for no mismatch Special case : NV1=NV2 for identical devices Process variation effects: PVE (global+local var.) Random effects : RE Nominal values : NV Mismatch ratio : MR Mismatch = Δ( global + local + random var.) between transistors * MR able to provide a universal degree of influence

16. Accomplishments in this work : *Devised mismatch prediction methods for key steps of analog design flow *Improved simulation methods for mismatch *Devised methods to relate the mismatch effects between low level process and high level circuit parameters Executive Summary

17. Layout Optimizations -Effective for local variations, but of limited relevance to random variations -Balancing interconnect between two transistors still an open issue -Suffers linear optimization limitations as transistors rectangular, yet physical parameter distributions have curves Common centroid layout style Mismatch Compensation Methods Circuit Optimizations-Circuit specific and not easily generalizable -Usually process variations compensated instead of REs *Each method may require prediction of high level parameters, hence necessitating mismatch models iso-parameter lines for a physical parameter such as t ox t ox= 4.0nm t ox= 4.1nm t ox= 4.2nm

18. Previous Work on Mismatch Modeling BSIM parameter based models [M. Ismail et. al., ISCAS, 1993] -PCA used to assign weights, which represent a degree of influence to mismatch Electrical and/or empirical parameter attributed models [M. Pelgrom et. al., JSSC, 1989] -first order Taylor expansion Physics based models [Drennan et. al., IEDM, 1999] -relates mismatch constituents to physical attributes such as W, L, t ox, V FB, μ 0

19. Previous Work on Mismatch Modeling Physics based models - Current models overlook random effects and block communication + Mismatch is a physical phenomenon BSIM parameter based models - Dependence between parameters considered only by using first order correlations - Parameter inaccuracies due to extraction from wafer magnified through PCA - Successful use of PCA in image processing stems from parameters being physical sources Electrical and/or empirical parameter attributed models - Errors due to first order Taylor expansion - Pessimistic due to assumption of equal separation around nominal

20. Equal separation from nominal values? Improved predictions? Support for behavioral modeling? -Need to consider physical parameter based modeling Realistic models? Necessary Improvements to Mismatch Modeling Work -Causes non-optimal (pessimistic) mismatch prediction, yet same direction deviations from nominal should also be accounted for -Need to consider random effects both for manual design and CAD -Need statistical and accurate estimation Propagation between circuit blocks? -Need efficient and accurate techniques for inter-block propagation

21. Meeting current mismatch modeling challenges necessitates: -relating physical parameters to circuit parameters -imposition of hierarchy on parameters -measurement of the relationships between parameters *dependence graph *parameter levels *sensitivities Proposed Techniques -reduction of correlations between parameters *heuristic approach capable of correlation handling

22. Level 0: NSS NSUB : physical Level 1: e gap C ox : physical /electrical/mathematical Level 2: PHI ms GAMMA : physical/electrical/mathematical.. Level n: CMRR : electrical/mathematical P i,n = f i (P 1,0,P 2,0, P 3,1 …,P j,n-1 ) (n-1)’st level j’th parameter Levelization All parameters can be written as functions of parameters from previous levels. Classification of Parameters into Levels

23. gmgm Independent Normal Correlated? pdf? Level1 Level4 Level0 Level0 parameters independent, have Gaussian pdf Level Decomposition Example  n n V FB NSUBLW V th C ox t ox IDID k Level2 Level3 Correlated? pdf? Correlated? pdf? Correlated? pdf?

24. Connectivity Graphs Sensitivity determination at each edge suffices to construct sensitivities between transitively connected nodes Levels defined by maximum edge depth V th VT0 NSUB PHI V th =f3(PHI,VT0) V th =f4(NSUB) VT0=f2(PHI,NSUB) PHI=f1(NSUB) L1 L0 L2 L3 S V th = S V th * S PHI + S V th * ( S VT0 + S VT0 * S PHI ) NSUB PHI NSUB VT0 NSUB PHI NSUB

25. Bridging Physical Aspects to Circuit Parameters circuit parameters design parameters SPICE parameters L0 L1 L2 L3 L4 L5 L6 L7 L8 gmgm CMRR r out WLNSSTNSUBT OX C OX GAMMA PHI e gap Vth Id PHI ms VFB VT0

26. Connectivity Based Traversal -Proposed heuristic reduces the deteriorating effects of correlation in estimating an unknown sensitivity V th VT0 NSUB PHI V th =f3(PHI,VT0) V th =f4(NSUB) VT0=f2(PHI,NSUB) VT0=f1(NSUB) L1 L0 L2 L3 S V th = S V th * S PHI + S V th * ( S VT0 + S VT0 * S PHI ) NSUB PHI NSUB VT0 NSUB PHI NSUB

27. Connectivity Based Traversal -Proposed heuristic reduces the deteriorating effects of correlation in estimating an unknown sensitivity V th VT0 NSUB PHI V th =f3(PHI,VT0) V th =f4(NSUB) VT0=f2(PHI,NSUB) VT0=f1(NSUB) L1 L0 L2 L3 S V th = S V th * S PHI + S V th * ( S VT0 + S VT0 * S PHI ) NSUB PHI NSUB VT0 NSUB PHI NSUB

28. Connectivity Based Traversal -Proposed heuristic reduces the deteriorating effects of correlation in estimating an unknown sensitivity V th VT0 NSUB PHI V th =f3(PHI,VT0) V th =f4(NSUB) VT0=f2(PHI,NSUB) VT0=f1(NSUB) L1 L0 L2 L3 S V th = S V th * S PHI + S V th * ( S VT0 + S VT0 * S PHI ) NSUB PHI NSUB VT0 NSUB PHI NSUB

29. Connectivity Based Traversal -Proposed heuristic reduces the deteriorating effects of correlation in estimating an unknown sensitivity V th VT0 NSUB PHI V th =f3(PHI,VT0) V th =f4(NSUB) VT0=f2(PHI,NSUB) VT0=f1(NSUB) L1 L0 L2 L3 S V th = S V th * S PHI + S V th * ( S VT0 + S VT0 * S PHI ) NSUB PHI NSUB VT0 NSUB PHI NSUB

30. Proposed Methods for Various Design Steps Manual Method Simulation-based Method Monte Carlo-based Method Pdf from previous block included *Early design estimation methods (manual&simulation-based) save valuable time by decreasing iterations *Accurate simulations (simulation and MC-based) avoid lengthy design house – foundry iterations Provides a pdf instead of worst-case values Random effects considered

31. Mismatch EDA Tool Requirements Manual design Select architecture and technology SPICE simulations Behavioral level design and simulations Optimizations Test & diagnosis after production Manual mismatch prediction method Accurate simulation for mismatch Mismatch Predictive models

32. Manual design Select architecture and technology SPICE simulations Behavioral level design and simulations Optimizations Test & diagnosis after production Manual method Simulation and MC-based methods Manual and MC-based methods Mismatch EDA Tool Requirements

33. Mismatch Estimation Techniques Manual Simulation based Monte Carlo based Common Goal: Want to know the pdf of a circuit parameter Estimation based on circuit design formulas More accurate estimation based on simulations Promising for test, diagnosis and behavioral modeling *Methods cover a spectrum of design needs *Improvement attained at the expense of considerable increase in time overhead Mismatch cannot be effectively handled in terms of worst-case limits, as the pessimistic bounds do not consistently coincide Can be automated using symbolic analyzers

34. ref current mirror M1 M2 1 P i + 1 P i-RE 2 P i + 2 P i-RE 2 dep Overview of the Manual Method -Use analytic formulas and connectivity graphs to find sensitivities of each edge -Use these sensitivities to construct sensitivity of circuit parameters to physical parameters -Estimate pdf of the circuit parameter M3 3 P i + 3 P i-RE 3 dep I dep L ref. W dep V GS dep - VT0 dep -γ dep. ( 2PHI dep -V SB dep - 2PHI dep ) I ref L dep. W ref V GS ref - VT0 ref -γ ref. ( 2PHI ref -V SB ref - 2PHI ref ) How is pdf propagation achieved? Signal from previous block (e.g. bandgap reference) also included

35. Application of the Manual Method G  n1 V FB1 NSUB 1 L1L1 W1W1 V th1 C ox1 t ox1 I D1 k1k1 g m1  n2 V FB2 NSUB 2 L2L2 W2W2 V th2 C ox2 t ox2 I D2 k2k2 g m2 -Connectivity graph duplicated for each transistor in the mismatch group enabling the use of accurate symbolic formulas and accounting REs -Sensitivities calculated for each edge S G g m2 S I D2 g m2 NSUB1 g m1 I D1 k 1 k 1  n1 S G = S G * ( S g m1 * S I D1 + S g m1 ) * S k 1 -Other sensitivities calculated using connectivity based traversals

36. Application of the Manual Method G  n1 V FB1 NSUB 1 L1L1 W1W1 V th1 C ox1 t ox1 I D1 k1k1 g m1  n2 V FB2 NSUB 2 L2L2 W2W2 V th2 C ox2 t ox2 I D2 k2k2 g m2 -Connectivity graph duplicated for each transistor in the mismatch group enabling the use of accurate symbolic formulas and accounting REs -Sensitivities calculated for each edge S G g m2 S I D2 g m2 NSUB1 g m1 I D1 k 1 k 1  n1 S G = S G * ( S g m1 * S I D1 + S g m1 ) * S k 1 -Other sensitivities calculated using connectivity based traversals

37. Application of the Manual Method G  n1 V FB1 NSUB 1 L1L1 W1W1 V th1 C ox1 t ox1 I D1 k1k1 g m1  n2 V FB2 NSUB 2 L2L2 W2W2 V th2 C ox2 t ox2 I D2 k2k2 g m2 -Connectivity graph duplicated for each transistor in the mismatch group enabling the use of accurate symbolic formulas and accounting REs -Sensitivities calculated for each edge S G g m2 S I D2 g m2 NSUB1 g m1 I D1 k 1 k 1  n1 S G = S G * ( S g m1 * S I D1 + S g m1 ) * S k 1 -Other sensitivities calculated using connectivity based traversals

38. Application of the Manual Method G  n1 V FB1 NSUB 1 L1L1 W1W1 V th1 C ox1 t ox1 I D1 k1k1 g m1  n2 V FB2 NSUB 2 L2L2 W2W2 V th2 C ox2 t ox2 I D2 k2k2 g m2 -Connectivity graph duplicated for each transistor in the mismatch group enabling the use of accurate symbolic formulas and accounting REs -Sensitivities calculated for each edge -pdf of gain estimated while correlation effects substantially eradicated S G g m2 S I D2 g m2 NSUB1 g m1 I D1 k 1 k 1  n1 S G = S G * ( S g m1 * S I D1 + S g m1 ) * S k 1 -Other sensitivities calculated using connectivity-based traversals

39. Application of the Manual Method G  n1 V FB1 NSUB 1 L1L1 W1W1 V th1 C ox1 t ox1 I D1 k1k1 g m1  n2 V FB2 NSUB 2 L2L2 W2W2 V th2 C ox2 t ox2 I D2 k2k2 g m2 -Connectivity graph duplicated for each transistor in the mismatch group enabling the use of accurate symbolic formulas and accounting REs -Sensitivities calculated for each edge -pdf of gain estimated while correlation effects substantially eradicated S G g m2 S I D2 g m2 NSUB1 g m1 I D1 k 1 k 1  n1 S G = S G * ( S g m1 * S I D1 + S g m1 ) * S k 1 -Other sensitivities calculated using connectivity based traversals

40. Application of the Manual Method G  n1 V FB1 NSUB 1 L1L1 W1W1 V th1 C ox1 t ox1 I D1 k1k1 g m1  n2 V FB2 NSUB 2 L2L2 W2W2 V th2 C ox2 t ox2 I D2 k2k2 g m2 * Independent probability distributions assumed  physical parameters * μ and σ of highest level parameter estimated using connectivity graphs. Connectivity based traversal substantially reduces correlation effects  σ G = Σ S G *  σ P i  μ G = Σ S G *  μ P i where P i is i th physical parameter μiσiμiσi μiσiμiσi  g m2 S G g m1 S I D2 g m2  I D2 g m2 I D2

41. Simulation Method *Use direct simulation to find sensitivities of circuit parameters to physical parameters for improved accuracy G  n1 V FB1 NSUB 1 L1L1 W1W1 t ox1  n2 V FB2 NSUB 2 L2L2 W2W2 t ox2 V th1 C ox1 I D1 k1k1 g m1 V th2 C ox2 I D2 k2k2 g m2 *Simulator-aided version of the manual method

42. Simulation Method *Use direct simulation to find sensitivities of circuit parameters to physical parameters for improved accuracy *Simulator-aided version of the manual method G  n1 V FB1 NSUB 1 L1L1 W1W1 t ox1  n2 V FB2 NSUB 2 L2L2 W2W2 t ox2 *Improving over earlier physics based prediction methods: S G t ox2 Accounts for correlations from previous circuit blocks

43. Differential stage biased with current mirror I ref G1G1 Monte Carlo-Based Method *Assign independent physical parameter distributions to mismatch groups *Activate groups separately; each group assigned own SPICE parameters *Discard dominated groups; repeat for combinations of dominant groups to estimate pdf of a high level parameter G2G2 G3G3

44. Experimental Verification -Use direct simulation to find sensitivities of circuit parameters to physical parameters for improved accuracy I D1 M1 I D2 pdf from previous block included sim. method MC results Comparison of the Manual method with MC Simulations bin probability vs. current M2 S id 2 id 1 S id 2 L 1 0.7440-0.63000.3333-0.1780-0.04000.10130.8600 S id 2 W 1 S id 2 TOX 1 S id 2 UO 1 S id 2 XJ 1 S id 2 NCH 1 S id 2 L 2 -0.78600.6480-0.34660.17800.0433-0.1013 S id 2 W 2 S id 2 TOX 2 S id 2 UO 2 S id 2 XJ 2 S id 2 NCH 2

45. Differential stage biased with current mirror I ref G1G1 pdf of gain Simulation Results

46. Differential stage biased with current mirror I ref G2G2 G3G3 pdf of gain Simulation Results

47. Differential stage biased with current mirror I ref Simulation Results G2G2 G3G3 G1G1 High level circuit parameters may not exhibit a Gaussian-like pdf when physical input parameters are assigned independent Gaussian distributions. pdf of gain

48. Sense Amplifier CLK M2 M3 M4 M5 M1 Dependence of gain to variations in M4 @800MHz Higher level circuit parameters and large variations indicate highly non-linear relationships Gain vs NCH Gain vs T OX Gain vs W Insights for Future Modeling

49. Sense Amplifier CLK M2 M3 M4 M5 M1 Dependence of gain to variations in M3 @800MHz Gain vs NCH Gain vs T OX Gain vs W Further improvements on Manual and simulation- based estimation methods include optimizations for larger perturbations and their effect on higher circuit parameters Insights for Future Modeling

50. Concluding Remarks -Random effects involved in mismatch emphasized -Accurate conveying of mismatch information through connectivity-based traversals from transistor level to high level circuit design parameters presented -A manual mismatch prediction method discussed -Simulation and Monte Carlo-based mismatch measurement methods outlined -Conveying mismatch information between circuit blocks as a pdf signal introduced