1. Embedded Hardware and Software Self-Testing Methodologies for Processor Cores Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, and Ying Chen Design Automation Conference, 2000 Page(s): 625~630 Presented by Kao, Chung-Fu

2. 10/23/2000 2 What’s the Problems ? Current external testers vs. GHz processors. –Test speed, equipment cost ($20 million) Does hardware BIST good enough ? Why not Software-Based Self-Testing. –Low cost, high-quality self-test methodology

3. 10/23/2000 3 Outline Introduction Two case: PARWAN and PicoJava-II processor cores –Proof that hardware BIST still has many limitations Demonstrate that software-based self- testing methodology is a better approach Experiment and conclusion

4. 10/23/2000 4 Introduction Generate the required test patterns on-chip –At-speed testing, reduce the cost Built-In Self-Test (BIST) –Use for memory logic due to regular structure How to test non-memory parts ? Software-based self-testing

5. 10/23/2000 5 Preliminary The commercial logic BIST tool: LBIST –Applying BIST to two processor cores The design-under-test often has to be modified extensively to be random pattern testable

6. 10/23/2000 6 Case Study I: PARWAN We should modify the design in order to make the application of LBIST effective. 1.Splitting all bi- directional pins into separate I/O pins 2.Replacing all tri-state buffers with selectors 3.Inserting test points to improve the testability of the circuit

7. 10/23/2000 7 Experiment Area [gate count] Delay [ns] # Test patterns Fault coverage Original Modified Full Scan* LBIST* LBIST** 882 812 909 2185 2246 70.06 82.50 82.87 104.42 -- 640 32767 -- 89.39% 88.69% 97.34% * On the modified circuit ** On the modified circuit with test points LFSR, MISR, boundary scan Use test points

8. 10/23/2000 8 Case Study II: PicoJava-II LFSR Size MISR Size # Test pointArea Overhead # Test Patterns Fault coverage ControlObserve Full Scan LBIST-1 LBIST-2 LBIST-3 LBIST-4 -- 24 32 24 -- 41 -- 0 100 -- 0 100 11.13% 13.06% 13.29% 13.30% 12736 32767 1,000,000 95.54% 58.81% 82.53% 82.93% 84.11%

9. 10/23/2000 9 Software-Based Self-Testing Uses a software tester embedded in the processor memory For test generation and test application Advantages –Programmability; –Flexibility; –Generates desirable random test sets on-chip –No need of scan chains and boundary scan

10. 10/23/2000 10 The Software-Based Self- Testing Methodology The self-testing scheme includes two steps –Test preparation step –Self-testing step

11. 10/23/2000 11 Step 1: Component Test Preparation The test need of the component by a self-test signature –The seed (S) –The configuration (C) –The number of test patterns to be generated (N) Instruction-based testing

12. 10/23/2000 12 Instruction-Imposed Constraints Spatial constraints Temporal constraints SHU 4 8 4 8 in_flag (vcnz) data_in out_flag data_out asl asr Hardware paths involved in testing the SHU Ex: 1.asl and asr can not be both 1, 2.z and n must be consistent with data_in, 3.v = xor (c, sign_bit (data_in) )

13. 10/23/2000 13 Constraint Modeling Spatial constrain –Random patterns used on independent inputs Temporal constrain –As figure shown

14. 10/23/2000 14 Step 2: On-Chip Self-Test Uses an embedded software tester for the on-chip generation

15. 10/23/2000 15 Test Generation Program Using pseudo random number generator The S/W program emulating a H/W LFSR (Linear Feedback Shift Register) Q = S Do N times begin AC = Bitwise-and (C, Q); New_bit = Parity (AC); Q = New_bit : (Q >> 1); end external XOR gate polynomial = 101 (1+x 2 ) Seed (011) Hardware Implementation

16. 10/23/2000 16 Test Application Program Outputs observation –Data outputs –Status outputs 0 lda addr (y)// load AC 1 add addr (x) 2 sta data_out// store AC 3 lda 11111111 4 brav ifv// branch if overflow 5 and 11110111 6 label ifv brac ifc// branch if carry 7 and 11111011 8 label ifc braz ifz// branch if zero 9 and 11111101 10 label ifz bran ifn// branch if negative 11 and 11111110 12 label ifn sta flag_out

17. 10/23/2000 17 Experimental Results Test evaluation framework Prepares a VHDL test bench containing the initialized instruction memory and data memory Run the test bench, and captures the input signals to the processor. These are the test vectors to be applied during fault simulation

18. 10/23/2000 18 Experimental Results (cont’d) TPG*Test ApplicationTotal ALUSHUPC # instructions Prog. Size [byte] Exec. Time [cycle] 46 87 87764 213 424 37686 243 471 11604 73 147 595 575 1129 137649 Component Fault Coverage Processor Fault Coverage ACIRPCMARSRALUSHUCTRLDP I/FCPU I/F 99.3398.6189.1697.2298.8898.4894.0888.2671.5797.1491.42 * Test pattern generation program

19. 10/23/2000 19 Conclusion Demonstrated some of the disadvantages associated with H/W-based BIST tech. We hope that no need to change design when insert the test mechanism. Software-based self-testing tech. had proposed –No hardware overhead –Save money