Presentation on theme: "HV MOSFET Modeling with HiSIM_HV"— Presentation transcript:
1HV MOSFET Modeling with HiSIM_HV Hiroshima UniversityHV MOSFET Modeling with HiSIM_HVBenchmarks and New DevelopmentsEhrenfried Seebacher, Mitiko Muira Matausch, Kund Molnar
2Presentation Overview Hiroshima University &Presentation OverviewHV TransistorCompact Modeling RequirementsHV transistor sub-circuit modeling (the reference)State of the art HV Transistor Compact ModelsHiSIM_HV 1.x and 2.xBenchmarking: DC, ACSummary
3FOMs for HV Transistor Modeling Hiroshima University &FOMs for HV Transistor ModelingRON (On Resistor) (high vgs, low vds, and temp.)IDSAT (Saturation Current) ?VT long & shortCgg & Cgd Miller CapAnalog parameter for long channel lengthRF Parameter FT, FMAX ?Model should at least demonstrate Process spec as good as possible
4HV CMOS Transistor Types Hiroshima University &HV CMOS Transistor TypesNwellIncreased junction breakdown voltage (BV) of the drain diffusion is achieved by using a deep drain wellPWELLPWELLNWELLSmall on-resistance and high BV are contrary effects.The optimization of the tradeoff betweenboth quantities is of major interest.LDMOS transistor LDD, simple structure up to 10-12V also used for RF applications.HV CMOS using special drain well for increasing the D-S and D-B breakdown voltage.Isolated oneHV PMOSNwellThe gate length is extended beyond the body-drainwell junction, which increases the junction BV.The gate acts as a field plate to bends the electric field.RESURFeffectQuasi-Saturation Effect.
5Sub-circuit Modeling Hiroshima University & Simple sub-circuit can be used for LDD transistors LDPMOS with less quasi-saturation effect.Symmetrical HV PMOS, less quasi-saturationUnsymmetrical HV MOS high quasi-saturation and length scaling effect.Substrate current injectionSymmetrical HV CMOS with all ugly features of HV CMOS you can imagine.
6Sub-circuit Model Features and Limitations Hiroshima University &Sub-circuit Model Features and LimitationsHV MOS Transistor Model Features:Basic geometrical and process-related aspects such as oxide thickness, junction depth, effective channel length and widthRON modelingQuasi saturation region and the saturation regionGeometry scaling, Short-channel effects1/f and thermal noise equationTemperature Modeling for RON, VT, IDSATHigh Voltage Parasitic ModelsBulk (Substrate) currentEffects of doping profiles, substrate effectModeling of weak, moderate and strong inversion behaviorParasitic bipolar junction transistor (BJT).Model Limitations:RF modelingSH modelingCgd, Cgg ……Graded channelImpact ionization in the drift regionHigh-side switch (sub-circuit extension needed).
7State of the Art HV Compact Models and new Developments Hiroshima University &State of the Art HV Compact Models and new DevelopmentsEKV HV TransistorUnder development within the EU Project COMON“A Physics-Based Analytical Compact Model for the Drift Region of the HV-MOSFET” Antonios Bazigos, François Krummenacher, Jean-Michel Sallese, Matthias Bucher, Ehrenfried Seebacher, Werner Posch, Kund Molnár, and Mingchun TangPSP HV – Transistor ModelIn development based on PSP surface potential modelMM20asymmetrical, surface-potential-based LDMOS model, developed by NXP ResearchHiSIM_HVCMC Standard model version and 1.2.1Version in evaluation
8Power MOSFET Application Range: a few volts ~ a few hundred volts Hiroshima University &Power MOSFETApplication Range: a few volts ~ a few hundred voltsDevice Structure: extension of conventional MOSFETsWide Possible Applications: freedom for circuit design8
9Extension of Bulk-MOSFET Model HiSIM2 Hiroshima University &Extension of Bulk-MOSFET Model HiSIM2Complete Surface-Potential-Based ModelfS0 : at source edgefSL : at the end of the gradual-channel approx.fS(DL) : at drain edge (calculated from fSL)Channel-Length ModulationOverlap CapacitanceBeyond Gradual-Channel ApproximationThe surface potentialsat the source (fS0), at the pinch-off point (fSL), at the channel/drain junction(fS(D L)), and at the drain contact (fS0+Vds) are determined, which are at the sametime implicit functions of the applied terminal voltages referenced to the sourcenode thus model-internal iteration procedures are required only for calculating fS0and fSL.
10HiSIM-HV a few hundred volts > Bias Range > a few volts Hiroshima University &HiSIM-HVa few hundred volts > Bias Range > a few volts(Asymmetric)(Symmetric)Verwendung von effectiven internen Spannungen; wird von jedem Terminal abgezogenVgs,eff = Vgs – Ids x RsVds,eff = Vds – Ids x (Rs + Rdrift )Vbs,eff = Vbs – Ids x Rspotential drop
11Consistent Modeling in Drift Region Ldrift Hiroshima University &Consistent Modeling in Drift RegionLdriftNdriftVDDPPotential drop in the drift regionVdsVDDP Interner KnotenY. Oritsuki et al., IEEE TED, 57, p. 2671, 2010.Y. Oritsuki et al., IEEE TED, 57, p. 2671, 2010.
12HiSIM reproduces fS(DL) calculated by 2D-device simulator. Hiroshima University &Key Potential Values: potential determining LDMOS characteristicsfS(DL)fS(DL) [V]Vgs [V]Vds [V]VDDPVDDPHVHVHiSIM reproduces fS(DL) calculated by 2D-device simulator.
13Modeling of Rdrift HiSIM_HV 1.0.0 Series Hiroshima University &Modeling of RdriftHiSIM_HV SeriesBias Dependence is modeled based on principle.Y. Oritsuki et al., IEEE TED, 57, p. 2671, 2010.
14Quasi-saturation behavior of LDMOS is reproduced. Hiroshima University &Accuracy Comparison of Ids-Vds: 2D-Device Simulation Results: HiSIM-HV ResultsId [A]Vgs=2.5VVgs=5VVgs=7.5VVgs=10Vgd [S]Quasi-saturation behavior of LDMOS is reproduced.
15Current-Voltage Characteristics Hiroshima University &Current-Voltage CharacteristicsRelatively Low Breakdown VoltageRelatively High Breakdown Voltage
16Empirical Model: Issues Hiroshima University &Empirical Model: IssuesIds - VgsConditions Parameter RDVG11 und RDVG12 (extreme transistor nmos50t)unphysical behavior Result of the empirical modelGm vs. VgsCare must be taken when adjusting critical parameters describing the Vgs dependence.
17Model Benchmark Output Characteristic Hiroshima University &Model Benchmark Output CharacteristicHiSIM_HV v. BSIM3v3 Subcircuit
18Capacitance-Voltage Characteristics Hiroshima University &Capacitance-Voltage CharacteristicsNormal MOSFETCapacitance [fF]Vgs [V]-4-2242.01.81.20.80.4CgbCggCgdCgsVds=0VAsymmetrical LDMOSSymmetrical HVMOSDerivation of Cgd=-dQg/dVd
19AC Modeling: Cgg BSIM3+JFETS Subckt. HiSIM_HV Hiroshima University &AC Modeling: CggBSIM3+JFETS Subckt.HiSIM_HVSubcircuit: bad fitting quality, especially in accumulation.HiSIM_HV: good fitting quality in all regions.
20Self-Heating Effect for DC Analysis Hiroshima University &Self-Heating Effect for DC Analysis
21Self-Heating Effect for AC Analysis Hiroshima University &Self-Heating Effect for AC AnalysisRC-Network:Dynamical behaviour using the thermical capacitance; green room temperature; Device temperature increase of 80deg
22Modeling Rdrift HiSIM_HV 2.0.0 Series MOSFET + Resistor MOSFET Hiroshima University &Modeling RdriftHiSIM_HV SeriesMOSFET + ResistorMOSFETResistorDPChannelDP internal Note: Spliting in two parts; Hisim2 & Drift resistor
23Node potential Vddp is solved iteratively. Hiroshima University &Node potential Vddp is solved iteratively.Equivalent circuit with internatl note DP;Parameter Meaning: xx; Xov; Ndrift; udrift; RDRLOWVD1,2&RDRQOVER, b3version ist im xx term enthalten
24Velocity saturation affects strongly on I-V characteristics. Hiroshima University &I-V Characteristics of Resistor2D-Device SimulationIddpU drift wird mit vmax drift beschriebenLadungsträger Geschwindigkeits Sättigung Effekt in der Drift Region beeinflusst sehr stark die IV Charakteristik besonders bei hohen Spannungen.Additionally Velocity saturation modeling in the Drift region. Parameter RDRVMAXxx which is length and width dependent.VDDPVelocity saturation affects strongly on I-V characteristics.
25Modeling Current-Flow in Overlap Region Hiroshima University &Modeling Current-Flow in Overlap RegionLoverW0WdepxdepDjuncWjuncxovxjuncxjuncxdepDjuncA: junction depth: current exude coefficient intodepletion regionGeometrical Explanation for the drift region modelingVddp
26Drift-Resistance Model: New Physical Model in ver.2.0.0 Hiroshima University &Drift-Resistance Model: New Physical Model in ver.2.0.0Old empirical model: still available (CORDRIFT=0)New physical model (CORDRIFT=1) : drift-current in the drift region:Xov is the effective depth of the drift region:W0: un-modulated drift region depthWdep: depth limitation due to ΦSWjunc: depth limitation due to substrate/drift junction (high-side switch effect)Wdep and Wjunc are a functions of NOVERNOVER is the impurity concentration in the drift-region affecting both DC and CV.W0Nover impact dc and AC behaviour be carefule26
27Verification of I-V Characteristics Hiroshima University &Verification of I-V Characteristics2D-Device Sim.HiSIM_HV(Lch = 1mm , Lover = 1mm, Djunc = 2mm)Vds = 0.5V, 2V, 5V, 10~30VId [mA]Id [mA]Vds = 0.5V, 2V, 5V, 10~30VVds = 0.5V, 2V, 5V, 10~30Vxov improvementsVgs [V]Vgs [V]The xov model enables to fit I-V characteristicsfor wide range of bias conditions.Id [mA]Id [mA]Vgs= 3~9V, 15V, 30VVgs= 3~9V, 15V, 30VVgs= 3~9V, 15V, 30VVds [V]Vds [V]
28Empirical Model vs. Physical Model: IdVg Hiroshima University &Empirical Model vs. Physical Model: IdVgHiSIM_HV 1.x.x Old EmpiricalHiSIM_HV 2.x.x New PhysicalIds - VgsGm vs. Vgs
29Empirical Model vs. Physical Model: IdVd Hiroshima University &Empirical Model vs. Physical Model: IdVdHiSIM_HV 1.x.x Old EmpiricalHiSIM_HV 2.x.x New Physical
30HiSIM_HV Release Hiroshima University & Was bedeutet ROT? Zuletzt aufgeladen?
31The Extreme Case; 120V Transistors Hiroshima University &The Extreme Case; 120V TransistorsHiSIM_HV v. BSIM3 sub-circuitHV NMOS output and transfer characteristic of a typical wafer. W/L=40/0.5,VGS= 2.9, 4.8, 6.7, 8.6, 10.5, 12.4, 14.3, 16.2, 18.1, 20 V, VBS=0 V. &VBS= 0, -1, -2, -3, -4 V, VDS=0.1 V.+ = measured, full lines= BSIM3v3 model; dashed lines = HiSIM_HV 1.2.1
32Isolated HVMOS: High-Side Switch Modeling Hiroshima University &Isolated HVMOS: High-Side Switch Modeling- HVMOS used on the low-side of a load:Source and Substrate hold at the same potential- HVMOS used on the high-side of a load:Both Source and Drain can be placed at high potential=> Ron is changing with Vsub-sVsub=0Vsub=-120VTransfer CharacteristicsVd=0.1V, Vs=Vb=0HiSIM_HV 1.2.1: Vsub modulates the effective depth of the drift region: Rdrift(Vsub,s)
33HiSIM_HV The following effects are also included: Hiroshima University &HiSIM_HVThe following effects are also included:Depletion effect of the gate polycrystalline silicon (poly-Si).Quantum mechanicalCLMNarrow channelSTILeakage currents (gate, substrate and gate-induced drain leakage (GIDL) currents).Source/bulk and drain/bulk diode models.Noise models (1/f, thermal noise, induced gate noise).Non-quasi static (NQS) model.Complete Surface potential-based:HiSIM_HV solves the Poisson equation along the MOSFETchannel iteratively,including the resistance effect in the drift region.high flexibility20 model flagsscales with the gate width,the gate length,the number of gate fingersand the drift region length.In addition, HiSIM_HV is capable of modelingsymmetric and asymmetric HV devices.
34SummaryDecision for HV Model depends very much on the application Sub-circuit approach is very flexible and usable for switching applications and for analog applications using large transistors sizes. HiSIM_HV and shows high accuracy for all benchmarks. Detailed know how in parameter extraction needed Extensive measurements necessary. HiSIM_HV 2.x First Version New physical drift region model is under evaluation and shows excellent benchmark results.