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**HV MOSFET Modeling with HiSIM_HV**

Hiroshima University HV MOSFET Modeling with HiSIM_HV Benchmarks and New Developments Ehrenfried Seebacher, Mitiko Muira Matausch, Kund Molnar

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**Presentation Overview**

Hiroshima University & Presentation Overview HV Transistor Compact Modeling Requirements HV transistor sub-circuit modeling (the reference) State of the art HV Transistor Compact Models HiSIM_HV 1.x and 2.x Benchmarking: DC, AC Summary

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**FOMs for HV Transistor Modeling**

Hiroshima University & FOMs for HV Transistor Modeling RON (On Resistor) (high vgs, low vds, and temp.) IDSAT (Saturation Current) ? VT long & short Cgg & Cgd Miller Cap Analog parameter for long channel length RF Parameter FT, FMAX ? Model should at least demonstrate Process spec as good as possible

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**HV CMOS Transistor Types**

Hiroshima University & HV CMOS Transistor Types Nwell Increased junction breakdown voltage (BV) of the drain diffusion is achieved by using a deep drain well PWELL PWELL NWELL Small on-resistance and high BV are contrary effects. The optimization of the tradeoff between both quantities is of major interest. LDMOS transistor LDD, simple structure up to 10-12V also used for RF applications. HV CMOS using special drain well for increasing the D-S and D-B breakdown voltage. Isolated one HV PMOS Nwell The gate length is extended beyond the body-drain well junction, which increases the junction BV. The gate acts as a field plate to bends the electric field. RESURFeffect Quasi-Saturation Effect.

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**Sub-circuit Modeling Hiroshima University &**

Simple sub-circuit can be used for LDD transistors LDPMOS with less quasi-saturation effect. Symmetrical HV PMOS, less quasi-saturation Unsymmetrical HV MOS high quasi-saturation and length scaling effect. Substrate current injection Symmetrical HV CMOS with all ugly features of HV CMOS you can imagine.

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**Sub-circuit Model Features and Limitations**

Hiroshima University & Sub-circuit Model Features and Limitations HV MOS Transistor Model Features: Basic geometrical and process-related aspects such as oxide thickness, junction depth, effective channel length and width RON modeling Quasi saturation region and the saturation region Geometry scaling, Short-channel effects 1/f and thermal noise equation Temperature Modeling for RON, VT, IDSAT High Voltage Parasitic Models Bulk (Substrate) current Effects of doping profiles, substrate effect Modeling of weak, moderate and strong inversion behavior Parasitic bipolar junction transistor (BJT). Model Limitations: RF modeling SH modeling Cgd, Cgg …… Graded channel Impact ionization in the drift region High-side switch (sub-circuit extension needed).

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**State of the Art HV Compact Models and new Developments**

Hiroshima University & State of the Art HV Compact Models and new Developments EKV HV Transistor Under development within the EU Project COMON “A Physics-Based Analytical Compact Model for the Drift Region of the HV-MOSFET” Antonios Bazigos, François Krummenacher, Jean-Michel Sallese, Matthias Bucher, Ehrenfried Seebacher, Werner Posch, Kund Molnár, and Mingchun Tang PSP HV – Transistor Model In development based on PSP surface potential model MM20 asymmetrical, surface-potential-based LDMOS model, developed by NXP Research HiSIM_HV CMC Standard model version and 1.2.1 Version in evaluation

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**Power MOSFET Application Range: a few volts ~ a few hundred volts**

Hiroshima University & Power MOSFET Application Range: a few volts ~ a few hundred volts Device Structure: extension of conventional MOSFETs Wide Possible Applications: freedom for circuit design 8

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**Extension of Bulk-MOSFET Model HiSIM2**

Hiroshima University & Extension of Bulk-MOSFET Model HiSIM2 Complete Surface-Potential-Based Model fS0 : at source edge fSL : at the end of the gradual-channel approx. fS(DL) : at drain edge (calculated from fSL) Channel-Length Modulation Overlap Capacitance Beyond Gradual-Channel Approximation The surface potentials at the source (fS0), at the pinch-off point (fSL), at the channel/drain junction (fS(D L)), and at the drain contact (fS0+Vds) are determined, which are at the same time implicit functions of the applied terminal voltages referenced to the source node thus model-internal iteration procedures are required only for calculating fS0 and fSL.

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**HiSIM-HV a few hundred volts > Bias Range > a few volts**

Hiroshima University & HiSIM-HV a few hundred volts > Bias Range > a few volts (Asymmetric) (Symmetric) Verwendung von effectiven internen Spannungen; wird von jedem Terminal abgezogen Vgs,eff = Vgs – Ids x Rs Vds,eff = Vds – Ids x (Rs + Rdrift ) Vbs,eff = Vbs – Ids x Rs potential drop

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**Consistent Modeling in Drift Region Ldrift**

Hiroshima University & Consistent Modeling in Drift Region Ldrift Ndrift VDDP Potential drop in the drift region Vds VDDP Interner Knoten Y. Oritsuki et al., IEEE TED, 57, p. 2671, 2010. Y. Oritsuki et al., IEEE TED, 57, p. 2671, 2010.

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**HiSIM reproduces fS(DL) calculated by 2D-device simulator.**

Hiroshima University & Key Potential Values : potential determining LDMOS characteristics fS(DL) fS(DL) [V] Vgs [V] Vds [V] VDDP VDDP HV HV HiSIM reproduces fS(DL) calculated by 2D-device simulator.

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**Modeling of Rdrift HiSIM_HV 1.0.0 Series**

Hiroshima University & Modeling of Rdrift HiSIM_HV Series Bias Dependence is modeled based on principle. Y. Oritsuki et al., IEEE TED, 57, p. 2671, 2010.

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**Quasi-saturation behavior of LDMOS is reproduced.**

Hiroshima University & Accuracy Comparison of Ids-Vds : 2D-Device Simulation Results : HiSIM-HV Results Id [A] Vgs=2.5V Vgs=5V Vgs=7.5V Vgs=10V gd [S] Quasi-saturation behavior of LDMOS is reproduced.

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**Current-Voltage Characteristics**

Hiroshima University & Current-Voltage Characteristics Relatively Low Breakdown Voltage Relatively High Breakdown Voltage

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**Empirical Model: Issues**

Hiroshima University & Empirical Model: Issues Ids - Vgs Conditions Parameter RDVG11 und RDVG12 (extreme transistor nmos50t) unphysical behavior Result of the empirical model Gm vs. Vgs Care must be taken when adjusting critical parameters describing the Vgs dependence.

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**Model Benchmark Output Characteristic**

Hiroshima University & Model Benchmark Output Characteristic HiSIM_HV v. BSIM3v3 Subcircuit

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**Capacitance-Voltage Characteristics**

Hiroshima University & Capacitance-Voltage Characteristics Normal MOSFET Capacitance [fF] Vgs [V] -4 -2 2 4 2.0 1.8 1.2 0.8 0.4 Cgb Cgg Cgd Cgs Vds=0V Asymmetrical LDMOS Symmetrical HVMOS Derivation of Cgd=-dQg/dVd

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**AC Modeling: Cgg BSIM3+JFETS Subckt. HiSIM_HV**

Hiroshima University & AC Modeling: Cgg BSIM3+JFETS Subckt. HiSIM_HV Subcircuit: bad fitting quality, especially in accumulation. HiSIM_HV: good fitting quality in all regions.

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**Self-Heating Effect for DC Analysis**

Hiroshima University & Self-Heating Effect for DC Analysis

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**Self-Heating Effect for AC Analysis**

Hiroshima University & Self-Heating Effect for AC Analysis RC-Network: Dynamical behaviour using the thermical capacitance; green room temperature; Device temperature increase of 80deg

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**Modeling Rdrift HiSIM_HV 2.0.0 Series MOSFET + Resistor MOSFET**

Hiroshima University & Modeling Rdrift HiSIM_HV Series MOSFET + Resistor MOSFET Resistor DP Channel DP internal Note: Spliting in two parts; Hisim2 & Drift resistor

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**Node potential Vddp is solved iteratively.**

Hiroshima University & Node potential Vddp is solved iteratively. Equivalent circuit with internatl note DP; Parameter Meaning: xx; Xov; Ndrift; udrift; RDRLOWVD1,2&RDRQOVER, b3version ist im xx term enthalten

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**Velocity saturation affects strongly on I-V characteristics.**

Hiroshima University & I-V Characteristics of Resistor 2D-Device Simulation Iddp U drift wird mit vmax drift beschrieben Ladungsträger Geschwindigkeits Sättigung Effekt in der Drift Region beeinflusst sehr stark die IV Charakteristik besonders bei hohen Spannungen. Additionally Velocity saturation modeling in the Drift region. Parameter RDRVMAXxx which is length and width dependent. VDDP Velocity saturation affects strongly on I-V characteristics.

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**Modeling Current-Flow in Overlap Region**

Hiroshima University & Modeling Current-Flow in Overlap Region Lover W0 Wdep xdep Djunc Wjunc xov xjunc xjunc xdep Djunc A : junction depth : current exude coefficient into depletion region Geometrical Explanation for the drift region modeling Vddp

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**Drift-Resistance Model: New Physical Model in ver.2.0.0**

Hiroshima University & Drift-Resistance Model: New Physical Model in ver.2.0.0 Old empirical model: still available (CORDRIFT=0) New physical model (CORDRIFT=1) : drift-current in the drift region: Xov is the effective depth of the drift region: W0: un-modulated drift region depth Wdep: depth limitation due to ΦS Wjunc: depth limitation due to substrate/drift junction (high-side switch effect) Wdep and Wjunc are a functions of NOVER NOVER is the impurity concentration in the drift-region affecting both DC and CV. W0 Nover impact dc and AC behaviour be carefule 26

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**Verification of I-V Characteristics**

Hiroshima University & Verification of I-V Characteristics 2D-Device Sim. HiSIM_HV (Lch = 1mm , Lover = 1mm, Djunc = 2mm) Vds = 0.5V, 2V, 5V, 10~30V Id [mA] Id [mA] Vds = 0.5V, 2V, 5V, 10~30V Vds = 0.5V, 2V, 5V, 10~30V xov improvements Vgs [V] Vgs [V] The xov model enables to fit I-V characteristics for wide range of bias conditions. Id [mA] Id [mA] Vgs= 3~9V, 15V, 30V Vgs= 3~9V, 15V, 30V Vgs= 3~9V, 15V, 30V Vds [V] Vds [V]

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**Empirical Model vs. Physical Model: IdVg**

Hiroshima University & Empirical Model vs. Physical Model: IdVg HiSIM_HV 1.x.x Old Empirical HiSIM_HV 2.x.x New Physical Ids - Vgs Gm vs. Vgs

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**Empirical Model vs. Physical Model: IdVd**

Hiroshima University & Empirical Model vs. Physical Model: IdVd HiSIM_HV 1.x.x Old Empirical HiSIM_HV 2.x.x New Physical

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**HiSIM_HV Release Hiroshima University & Was bedeutet ROT?**

Zuletzt aufgeladen?

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**The Extreme Case; 120V Transistors**

Hiroshima University & The Extreme Case; 120V Transistors HiSIM_HV v. BSIM3 sub-circuit HV NMOS output and transfer characteristic of a typical wafer. W/L=40/0.5, VGS= 2.9, 4.8, 6.7, 8.6, 10.5, 12.4, 14.3, 16.2, 18.1, 20 V, VBS=0 V. & VBS= 0, -1, -2, -3, -4 V, VDS=0.1 V. + = measured, full lines= BSIM3v3 model; dashed lines = HiSIM_HV 1.2.1

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**Isolated HVMOS: High-Side Switch Modeling**

Hiroshima University & Isolated HVMOS: High-Side Switch Modeling - HVMOS used on the low-side of a load: Source and Substrate hold at the same potential - HVMOS used on the high-side of a load: Both Source and Drain can be placed at high potential => Ron is changing with Vsub-s Vsub=0 Vsub=-120V Transfer Characteristics Vd=0.1V, Vs=Vb=0 HiSIM_HV 1.2.1: Vsub modulates the effective depth of the drift region: Rdrift(Vsub,s)

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**HiSIM_HV The following effects are also included:**

Hiroshima University & HiSIM_HV The following effects are also included: Depletion effect of the gate polycrystalline silicon (poly-Si). Quantum mechanical CLM Narrow channel STI Leakage currents (gate, substrate and gate-induced drain leakage (GIDL) currents). Source/bulk and drain/bulk diode models. Noise models (1/f, thermal noise, induced gate noise). Non-quasi static (NQS) model. Complete Surface potential-based: HiSIM_HV solves the Poisson equation along the MOSFET channel iteratively, including the resistance effect in the drift region. high flexibility 20 model flags scales with the gate width, the gate length, the number of gate fingers and the drift region length. In addition, HiSIM_HV is capable of modeling symmetric and asymmetric HV devices.

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Summary Decision for HV Model depends very much on the application Sub-circuit approach is very flexible and usable for switching applications and for analog applications using large transistors sizes. HiSIM_HV and shows high accuracy for all benchmarks. Detailed know how in parameter extraction needed Extensive measurements necessary. HiSIM_HV 2.x First Version New physical drift region model is under evaluation and shows excellent benchmark results.

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