1. Subthreshold Logic Energy Minimization with Application- Driven Performance EE241 Final Project Will Biederman Dan Yeager

2. Outline Motivation and Introduction Problem Analysis Prior Work Proposed Solution Design Procedure Minimum Energy Tracking Loop Results

3. Motivation Emerging Markets: Wireless Sensors – Shipment tracking, biomedical electronics, environmental monitoring Fixed Computation -> Minimize E/op 10-year life applications (100k hrs) AAA Battery – > ~ 10 uA * Vdd

4. Introduction: Conventional MEP Lowering E/op – Lower V DD ! How Far? – Minimum Energy Point may not provide sufficient performance

5. Problem Analysis: F op Set by MEP F op set by MEP (V DD ) – F op can change with environment conditions (T) MEP doesn’t track with throughput demands – Wasted power during sleep or low computation

6. Problem Analysis: σ Vth Variation in Vth – LER & RDF Economics motivate continued technology scaling – ( Moore’s Law!! )

7. Prior Work: Adaptive F op Correlated Path Delay - Temp/Process - Critical path exceeds T clk Replica circuits can be used to compensate – ABB – AVS These circuits cannot adapt to uncorrelated V th variations from LER and RDF!

8. Prior Work: Dealing with σ Vth σ Vth due to LER/ RDF – Spatially Uncorrelated Upsizing- C increases Pipeline Depth- α decrease) Increase technology node (C increase & Moore’s Law)

9. Proposed Solution 1.Compensate for correlated temperature and process variation with an analog V TH sensor 2.Compensate for uncorrelated delay variation with timing error detection -> How do we optimize device sizing and pipeline depth in this regime?

10. Energy Optimization Delay is stochastic:

11. Energy Optimization Energy is also stochastic:

12. Energy Optimization Its all pretty messy… how do we optimize? 1.Yield – Pick a target yield -> sets conf, (# of sigma) – Allocate half of the yield to timing and half to energy – Y Total = √(Y Energy + Y timing ) 2.Design – MATLAB model to find optimal design parameters – Choose V dd_opt, V th_opt, n (pipeline logic depth), etc. 3.Power On – Our tracking loop ensures that all chips meet the timing constraint, but at the expense of energy – We can quickly pass / fail chips based on the supply voltage set by the tracking loop

13. Energy Tracking Loop

14. ABB (Adaptive Body Bias) Optimal Vdd, Vth at some process node, freq is constant Optimal body bias keeps Vth constant Optimal Body Bias at FF CornerOptimal Body Bias at SS Corner

15. Idea: Try to keep Vth constant vbn vbp sense Vdd/2 Vdd bias - + Charge Pump

16. Body Bias Correction Works! Process Corner Body Bias Voltage Temperature

17. DVS (Dynamic Voltage Scaling)

18. Tracking Loop Results – No ABB 300mV 175mV VDD = ERROR Pipeline In/Out Timing:

19. Tracking Loop Results – With ABB 225mV VDD = ERROR Pipeline In/Out Timing:

20. Conclusion Maximum energy efficiency -> subthreshold operation -> serious variability problems Correlated (P,T) vs. uncorrelated (RDF) variations – ex situ (replica) vs. in situ (timing detection) ABB and DVS can effectively provide optimal region of operation

21. References

22. Backup

23. Razor II Flip Flop Schematic

24. Razor II Timing

25. Energy Optimization We are concerned with the longest of p critical paths: