1. [M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Wed. Oct. 01 Overall Project Objective : Dynamic Control The Traffic Lights

2. Status  Design Proposal  Chip Architecture  Behavioral Verilog Implementation  Size estimates (Refined)  Floorplanning (Refined)  Behavioral Verilog simulated  Gate Level Design  Component Layout/Simulation  Chip Layout  Complete Simulation

3. Traffic Flows Sensors (Blue) To detect the car entered Sensors (Red) To detect the car leaved ARM 1 ARM 2

4. Traffic Light Flow Whenever pedestrian push the button, then this light will insert in the end of this cycle. ARM 1 ARM 2 Red GreenY Green (S traight + R ight )YRed+Green(L eft ) Red Y Green (S traight + R ight )YRed+Green(L eft )Y Phase A Phase C Phase BPhase APhase B ARM1 ARM2 PED We define three phases (A,B,C) for different operations.

5. SW – Switch light G – Green R – Red Y – Yellow T – Time for Yellow PED – Pedestrian SW (1bit) ARM (1bit) PED(1bit) CLK ARM1 [1:0] FSM Initial G.R Y.R R+L eft.R Y.R R.G R.Y R.R+L eft PED SW = 0 SW = 1 T < 2 T = 2 SW = 1 SW =0 T<10 PED = 1 T = 2 PED = 1 T = 2 T<= 2 SW = 0 T=15 T = 2 PED = 0 T = 2 PED = 0 ARM = 0ARM = 1 FSM For Lights Clear (1bit) ARM2 [1:0] PED(1bits) Blink T=10 T < 5 Complete(1bits)

6. Hold until n 1 or n 2 changes Light favors n 1 or n 2 ? n1n1 n2n2 T<r 1 ? T<r 2 ? T>= R 1 ?T>= R 2 ? n 1 =0? n 2 =0? f 1 <=0? f 2 <=0? Switch Light Reset T = 0 No Yes No Yes No Light favors arm 1 or arm 2 ? n1n1 n2n2 T<r left ? T>= R left ? No Yes No Yes No n 1 not change in T = 5? No Control reset Pedestrian For Green light For Red + Left T>= R p ? Yes No For Pedestrian n 2 not change in T = 5? n 1, n 2 :# of cars T :Time spent in this phase R i, r i : Max. and Min. time for each phase f i : the control function f 1 = α 1 *n 1 + β 1 – n 2 f 2 = α 2 *n 2 + β 2 – n 1

7.  f1 = α 1 *n 1 + β 1 – n 2  β= Σn*½*(1/Q) β : Floating Point  F1*Q = Q*α 1 *n 1 + Σn*½ – n 2 (Range for α : 1.0~2.0)  New Decision : Scaled by 8, instead 10  Why ? It save bit numbers to store value.  How ?  Maximum Value for 8*f*Q is about 2000 – Use 11 bits 001 → 0.125 100 → 0.625 To Store Value in α 010 → 0.250 101 →0.750 It can make sure there is no 010 → 0.375 110 → 0.875 floating point in 8*f1*Q 011 → 0.500 111 → 1.000 Need FPU ?

8. Arithmetic Unit  Addition – 11 bit  11-bit Ripple Carry Adder – 0* (308, reuse in mult)  Structual?  Done  Multiplication – 11 bit  Sequential Multiplier – 1000 transistors  Structual?  In progress

9. Sequential Mult Courtesy of Blanton-18340

10. Add and Shift algorithm  Set count = 11  Set AC and carryout to zero  Load multiplier and multiplicand(MD/MQ)  AC <= AC + MD * MQ  { carryout,AC,MQ} >> 1  count = count-1  Goto AC<= … till count = 0  done

11. User Input Q User Input R,r PED Input CLK AccumReg 1 11 ENTER 11 AccumReg 11 OUT / LEFT s0,s1: X 2 q0,q1: X 2 Reg X 10 11 Reg X 10 2:1 MUX 110 11 X 10 11 X 9 11 X 1 q0 q1 11 β n1 n0 11 Q_len11 16:1 MUX 4 Sel 11 s0 s111 Sel 4 N_avg αn 0 -n 1 αn 0 q 0 -s 0 q 1 -s 1 α0α0 α1α1 Q(αn 0 -n 1 ) FPU 2 Sel_FPU 1:16 De-MUX 4 Sel 11 110 Reg. 11 bit n0 n1 ROM 11 β 2:1 MUX 11 n_avg Q(αn 0 -n 1 ) q 1 -s 1 q 0 -s 0 αn 0 αn 0 -n 1 11 F α 0,α 1: X 2 ROM Reg 8X8 11 8 X 8 : Dot Line to Comparator R,r, RL,rl for Arm1 Arm2 11 ½ 2:1 MUX Reg PED11 Dot Lint to Comparator β 8 X 8 8 : 1 MUX INT. Compar 1 FSM SW ARM CLK Clear FSM 1 Complete ARM 1 ARM 2 PED1 2 2 ½ 11 ROM 11 User Input 2:1 MUX Reg 11 Accmu 81 Clk Div. 8 Accmu 8 F n0n0 n1n1 T 8 8 11 Reg 8 8 11 System Clock Real-Time Clock System Clock Real-Time Clock PED 8 8 1 1 1 1 1 1 R & r, R_L& r_L Sel_C 3 3 4X2 3X2 2 ALU MUX Block Diagram

12. Initial Values Clock Data Input PED Operation Initialize β To Comparator F, N 0, N 1 Selection T, F, N 0, N 1 R, r, R_ L, r_ l Output

13. Transistor Counts on Each Block T:154 X 2 T:308 X 2 T:132 X 2T:154 X 2 T:96T:896 T:96T:154 T:12 T:28T:112 T:308T:? T: 3080 T: 132 T: 1980 T: ~1000 T: 1980 T: 1540 T: 132 T: 924 T: ~400 T: ~3000 T: 450

14. Transistor Counts Estimates DevicesNumber of Transistors ALU~1000 Registers6830 MUX / DEMUX8508 Flow Control FSM~3000 Light Control FSM450 Accumulator1568 ROM~0 Comparator~400 (P.S. FPU: ~12000) Total~21756

15. Transistor Counts Estimates Number of Transistors ALU~10003353.4 Registers683022903.7 MUX / DEMUX850828530 Flow Control FSM~300010060.2 Light Control FSM4501509 Accumulator15685258.1 ROM-- Comparator~4001346.4 Total~2175672960.8 Area (um )Devices 2

16. Input Get q0 q1 s0 s1 Avg. q ½, Q_L ALUOutput Reuse F, Ni Give R,r Input PED, CLK Compare T Control Light ALU

17. Structure for Light control FSM D-FFs Combinational logic for next state Encoder Decoder next state [3:0] current state [3:0] Combinational logic for output Arm1 [1:0] Arm2 [1:0] PEDESTRIAN complete SW arm PED delay Delay signal generator CLK Y2R, PEDBLINK etc. Add another function block -delay gen- in FSM, since it’s needed to implement the function “repeat” in Verilog

18. Partial Combinational Logic for Next State

19. `include "gates.v" `include "lib.v" module decoder(s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, state); input [3:0] state; output s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10; wire c0_1, c0_2, c1_1, c1_2, c2_1, c2_2, c3_1, c3_2, c4_1, c4_2, c5_1, c5_2, c6_1, c6_2, c7_1, c7_2, c8_1, c8_2, c9_1, c9_2, c10_1,c10_2; wire [3:0] state_b; NOT inv1(state_b[0], state[0]); NOT inv2(state_b[1], state[1]); NOT inv3(state_b[2], state[2]); NOT inv4(state_b[3], state[3]); //encoder for s0 NAND2 s0_1(c0_1, state_b[0], state_b[1]); NAND2 s0_2(c0_2, state_b[2], state_b[3]); NOR2 s0_3(s0, c0_1, c0_2); //encoder for s1 NAND2 s1_1(c1_1, state[0], state_b[1]); NAND2 s1_2(c1_2, state_b[2], state_b[3]); NOR2 s1_3(s1, c1_1, c1_2); //encoder for s2 NAND2 s2_1(c2_1, state_b[0], state[1]); NAND2 s2_2(c2_2, state_b[2], state_b[3]); NOR2 s2_3(s2, c2_1, c2_2); //encoder for s3 NAND2 s3_1(c3_1, state[0], state[1]); NAND2 s3_2(c3_2, state_b[2], state_b[3]); NOR2 s3_3(s3, c3_1, c3_2); //encoder for s4 NAND2 s4_1(c4_1, state_b[0], state_b[1]); NAND2 s4_2(c4_2, state[2], state_b[3]); NOR2 s4_3(s4, c4_1, c4_2); //encoder for s5 NAND2 s5_1(c5_1, state[0], state_b[1]); NAND2 s5_2(c5_2, state[2], state_b[3]); NOR2 s5_3(s5, c5_1, c5_2); //encoder for s6 NAND2 s6_1(c6_1, state_b[0], state[1]); NAND2 s6_2(c6_2, state[2], state_b[3]); NOR2 s6_3(s6, c6_1, c6_2); //encoder for s7 NAND2 s7_1(c7_1, state[0], state[1]); NAND2 s7_2(c7_2, state[2], state_b[3]); NOR2 s7_3(s7, c7_1, c7_2); //encoder for s8 NAND2 s8_1(c8_1, state_b[0], state_b[1]); NAND2 s8_2(c8_2, state_b[2], state[3]); NOR2 s8_3(s8, c8_1, c8_2); //encoder for s9 NAND2 s9_1(c9_1, state[0], state_b[1]); NAND2 s9_2(c9_2, state_b[2], state[3]); NOR2 s9_3(s9, c9_1, c9_2); //encoder for s10 NAND2 s10_1(c10_1, state_b[0], state[1]); NAND2 s10_2(c10_2, state_b[2], state[3]); NOR2 s10_3(s10, c10_1, c10_2); endmodule module combi_next_state(out0, out1, out2, out3, out4, out5, out6, out7, out8, out9, out10, s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, arm, SW, PED, delay); output out0, out1, out2, out3, out4, out5, out6, out7, out8, out9, out10; input s0, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, arm, SW, PED, delay; wire arm_b, SW_b, PED_b, delay_b, w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12, w13, w14, w15, w16, w17, w18; NOT inv1(arm_b, arm); NOT inv2(SW_b, SW); NOT inv3(PED_b, PED); NOT inv4(delay_b, delay); AND2 a1(w1, delay, PED_b); AND2 a2(w2, delay, PED); NAND2 n1(w7, s4, w1); NAND2 n2(w9, s4,w2); NAND2 n3(w5, s8, w1); NAND2 n4(w10, s8, w2); NAND2 n5(w3, s0, arm_b); NAND2 n6(w4, s1, SW_b); NAND2 n7(w6, s0, arm); NAND2 n8(w8, s5, SW_b); Structure Verilog for Decoder and Combinational Logic (partial)

20. The output for decoder plus combinational logic modules. Next state did change according to the combinations of input and current state. Future work: the rest of three modules in FSM: Encoder, delay gen, and combinational logic for output. The simulation result

21. Question ?

22. Transistor Counts on Each Block T:154 X 2 T:308 X 2 T:132 X 2T:154 X 2 T:96T:896 T:96T:154 T:12 T:28T:112 T:308T:? T: 3080 T: 132 T: 1980 T: ~1000 T: 1980 T: 1540 T: 132 T: 924 T: ~400 T: ~3000 T: 450