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1ASM Algorithmic State Machines (ASM) part 1

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ASM2 Algorithmic State Machine (ASM) Our design methodologies do not scale well to real-world problems. Take this:

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ASM3 Algorithmic State Machine (ASM) Procedure for implementing a problem with a given piece of equipment. Define digital algorithmic solutions for hardware. Resembles a conventional flow chart but interpreted differently: – ASM described the sequence as well as the timing of events. – Adapted to specify the control sequence and data processing operations.

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ASM4 Control and datapath A digital system can be split into two components: Datapath unit: Manipulates data according to the system requirements. Control unit: Generates the signals for sequencing the operations in the data processor. Figure 8.2 Control and datapath interaction

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ASM5 State box Figure 8.3 ASM chart state box

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ASM6 Decision box Figure 8.4 ASM chart decision box

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ASM7 Conditional box

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ASM8 ASM block One entrance path Any number of exit paths Describes the state of the systems during one clock-pulse interval. The operations within the state and the conditional boxes are executed with a common clock pulse while the system is in state S_0.

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ASM9 ASM chart – State diagram

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ASM10 All the following operations occur simultaneously: – A A+1 – If E == 1 then R 0 – Depending on E and F, the state is changed to S_1, S_2 or S_3. Timing

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ASM11 Design problem Design a digital system with two flip-flops, E and F, and one 4-bit binary counter, A. The individual flip-flops of A are denoted by A4,A3,A2, and A1, with A4 holding the MSB. A start signal S initiates system operation by clearing the counter A and the flip-flop F. The counter is then incremented by 1 starting from the next clock pulse and continues to increment until the operations stop. Counter bits A3 and A4 determine the sequence of operations: – If A3 == 0, E is cleared to 0 and the count continues. – If A3 == 1, E is set to 1; then if A4 == 0, the count continues, but if A4 == 1, F is set to 1 on the next clock pulse and the system stops counting.

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ASM12 Design a digital system with two flip-flops, E and F, and one 4-bit binary counter, A. The individual flip-flops of A are denoted by A4,A3,A2, and A1, with A4 holding the MSB. A start signal S initiates system operation by clearing the counter A and the flip-flop F. The counter is then incremented by 1 starting from the next clock pulse and continues to increment until the operations stop. Counter bits A3 and A4 determine the sequence of operations: – If A3 == 0, E is cleared to 0 and the count continues. – If A3 == 1, E is set to 1; then if A4 == 0, the count continues, but if A4 == 1, F is set to 1 on the next clock pulse and the system stops counting. ASM Chart

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ASM13 Sequence of operations L1, L3 L2 L1L2L3

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ASM14 Sequence of operations

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ASM15 The datapath

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ASM16 State diagram for control

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ASM17 State table 10000XXX11T X10T X X0X XX100T XX000 T2T1T0G1G0A4A3SG1G0 Present state symbol OutputsNext state InputsPresent state

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ASM18 State table 10000XXX11T X10T X X0X XX100T XX000 T2T1T0G0G1A4A3SG0G1 Present state symbol OutputsNext state InputsPresent state D G1 = T 1 A 3 A 4 D G0 = T 0 S + T 1 T 0 = G 0 ’ T 1 = G 1 ’ G 0 T 2 = G 1

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ASM19

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20ASM Algorithmic State Machines (ASM) part 2

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ASM21 Binary multiplier How do we do multiplication by hand? In binary?

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ASM22 Datapath for binary multiplier Sum only two binary numbers accumulating the partial sums in Register Q. Instead of shifting the multiplicand to the left, shift the product to the right

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ASM23 P: the number of bits in the registers ASM for binary multiplier

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ASM24 Initial state Register B Register ARegister QC P =1 Z =0

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ASM25 Q0 = 1; add B – first partial product Register B Register ARegister QC P =1 Z =

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ASM26 Shift right CAQ Register B Register ARegister QC P =1 Z =0

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ASM27 Q0=1; add B – second partial product Register B Register ARegister QC P =1 Z =

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ASM28 Shift right CAQ Register B Register ARegister QC P =1 Z =0

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ASM29 Q0=0; Shift right CAQ Register B Register ARegister QC P =0=0 Z =0

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ASM30 Q0=0; Shift right CAQ Register B Register ARegister QC P =0=0 Z =0

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ASM31 Q0=1; add B – fifth partial product Register B Register ARegister QC P =1=1 Z =

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ASM32 Shift right CAQ Register B Register ARegister QC P =1=1 Z =1

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ASM33 Trace of the binary multiplication Final product in AQ = Shift right CAQ Fifth partial product Q0=1; add B Q0=0; shift right CAQ Q0=0; shift right CAQ Shift right CAQ Second partial product Q0=1; add B Shift right CAQ First partial product Q0 = 1; add B Multiplier in Q PQACInitial conditions : B=10111

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ASM34 Control Logic Signals to be generated: – T0-T3 – L (The Load signal for Register A, that allows the loading of the output of the binary adder.

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ASM35 Control Circuit implemented with D flip-flops + Dec

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ASM36 Making the design of the control logic easier Z=0

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ASM37 One FF per state T0 = T0 S’ + T3 Z T1 = T0 S T2 = T1 + T3 Z’ T3 = T2 Z=0

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ASM38 ASM with four control inputs Operations are left blank. We are interested in the design of the control part only. Four control inputs: w, x, y, z Four states: T0-T3 needs 2 flip-flops.

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ASM39 Using MUX’es to implement the control logic Two D flip- flops encode the state. The state is decoded into state signals T0-T3 by a decoder. The current state multiplexes the next state. Challenge: how to set the inputs of the MUX’es?

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ASM40 Multiplexer inputs G2 y’z’1111 Y0111 y’z+y’z’ = y’ y+y’z’ = y+z’ y’z1011 yz1101 yz’0101 yzyz’+yz = y y’0001 x’1110 1x0110 w1000 w0w’0000 MUX2MUX1G1 Multiplexer inputs Input conditions Next State Present state

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ASM41 The complete circuit

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ASM42 Count-of-Ones The system consists of two registers R1 and R2 and a flip-flop E. The system counts the number of 1’s in the number loaded into R1 and set R2 to that number. Shift one bit from R1 into E. If E == 1 then R2++ If Z = = 1 (that is R1 == 0) then stop. R2 is initialized to all 1’s. Why?

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ASM43 Datapath for Count-of-Ones

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ASM44 Multiplexer inputs G2 E’1011 E E None1101 Z’ Z0010 S1000 S0S’0000 MUX2MUX1G1 Multiplexer inputs Input conditions Next State Present state

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ASM45 Control logic for Count-of-Ones

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