1. Fast Logic Restructuring Using Node Merging and Node Addition and Removal Yung-Chih Chen 陳勇志 Department of Electrical Engineering Chung Yuan Christian University 1 2011/10/27

2. Outline  Introduction  Preliminaries  Node merging with don’t cares  Node addition and removal with don’t cares  Satisfiability-based bounded sequential equivalence checking  Conclusion 2 2011/10/27

3. Introduction  Node merging is a logic restructuring technique -Replace one node with another node in a logic circuit 3 2011/10/27 A B A B Circuit size reduction

4. Introduction  Two nodes can be correctly merged when -they are functionally equivalent, or -their functional differences are never observed at a primary output (PO) Observability Don’t Care (ODC) 4 2011/10/27

5. Example n3n3 n1n1 n2n2 n4n4 n5n5 n6n6 n7n7 n8n8 n9n9 n 10 n 12 n 13 n 11 x1x1 x2x2 x3x3 x4x4 n 6 and n 8 are not functionally equivalent Their values only differ when x 3 = 1 and x 2 = x 4 x 2 = x 4 implies n 7 = 0, n 7 = 0 blocks n 8 The functional differences of n 6 and n 8 are never observable n 8 can be replaced with n 6  And-Inverter Graph (AIG) 2011/10/27 5 1 1 0

6. Problem formulation  Given a target node n t, find other nodes called substitute nodes which can replace n t without changing the circuit’s functionality -Inputs: a circuit and a target node -Outputs: substitute nodes 6 2011/10/27

7. Previous works  Satisfiability (SAT)-based methods 7 2011/10/27 Full observability computation is VERY expensive Random simulation Candidate collection Merger checking ODC computation SAT solving

8. Previous works  Local ODC computation [1] -Compute local ODC within a bounded-depth k A node is observable when it is observable at the bounded- depth k -CPU time: controllable -Capability: exact when k is ∞, limited to k  Global ODC computation [2] -Compute global but approximate ODC -CPU time: time-consuming -Capability: not limited to local ODC but not exact 8 2011/10/27 [1] Q. Zhu, N. Kitchen, A. Kuehlmann, and A. Sangiovanni-Vincentelli, “SAT Sweeping with Local Observability Don’t Cares,” in Proc. Design Automation Conf., 2006, pp. 229-234. [2] S. Plaza, K. H. Chang, I. Markov, and V. Bertacco, “Node Mergers in the Presence of Don’t Cares,” in Proc. Asia South Pacific Design Automation Conf., 2007, pp. 414-419.

9. Our method  One sufficient condition for safely merging two nodes -ATPG-based approach  NO random simulation, NO ODC computation, NO candidates, and NO SAT solving -Run time: efficient  Also find functional equivalent and global ODC- based mergers -Capability: competitive 9 2011/10/27

10. Outline  Introduction  Preliminaries  Node merging with don’t cares  Node addition and removal with don’t cares  Satisfiability-based bounded sequential equivalence checking  Conclusion 10 2011/10/27

11. Stuck-at fault test  A stuck-at fault test -A process to find a test vector which generates different values in the fault-free and faulty circuit -A test vector exists → testable; otherwise, untestable  A test vector must activate and propagate the fault effect to a PO -generates n = 1 -propagates n = 1 to a PO 112011/10/27 stuck-at 0 1 1 1 1 1 1 0 1 1 nn

12. Mandatory assignment (MA)  Given a stuck-at fault, MAs are  unique value assignments to nodes required for a test vector to exist  MAs are necessary for detecting a stuck-at fault Consider n 8 ’s stuck-at 0 fault: n 8 =1, n 4 =0, n 3 =1, n 7 =1, n 2 =1, n 6 =1 are MAs n2n2 n3n3 n4n4 n6n6 n7n7 n8n8 n 11 x2x2 x3x3 x4x4 122011/10/27 stuck-at 0

13. Outline  Introduction  Preliminaries  Node merging with don’t cares  Node addition and removal with don’t cares  Satisfiability-based bounded sequential equivalence checking  Conclusion 13 2011/10/27

14. Node merging and misplaced wire error  Replacing n t with n s can be considered a misplaced wire error -The wires, w 1 ~ w 3, should be connected with n t instead of n s 14 2011/10/27 ntnt nsns w1w1 w2w2 w3w3 Correct circuit C ntnt nsns w1w1 w2w2 w3w3 Incorrect circuit C’

15. detects n t ’s stuck-at 1 fault and generates n s = 1 n s = 0 is necessary for detecting n t ’s stuck-at 1 fault A test vector of a replacement error  To detect a replacement error, a test vector must -1) generates n t ≠ n s, and generates n t = 1 and n s = 0, or generates n t = 0 and n s = 1 -2) propagates the value of n t to a PO ntnt nsns ntnt nsns detects n t ’s stuck-at 0 fault and generates n s = 0 n s = 1 is necessary for detecting n t ’s stuck-at 0 fault 15 2011/10/27

16. A sufficient condition  Condition: -n t can be replaced with n s -No test vector can generate n t ≠ n s, and propagate the value of n t to a PO simultaneously -n t can be replaced with INV(n s ) n s = 1 is necessary for detecting n t ’s stuck-at 0 fault, and n s = 0 is necessary for detecting n t ’s stuck-at 1 fault n s = 0 is an MA of n t ’s stuck-at 1 fault n s = 1 is an MA of n t ’s stuck-at 0 fault, and n s = 1 is an MA of n t ’s stuck-at 1 fault n s = 0 is an MA of n t ’s stuck-at 0 fault, and 16 2011/10/27

17. Example n1n1 n2n2 n3n3 n4n4 n5n5 n6n6 n7n7 n8n8 n9n9 n 10 n 12 n 13 n 11 x1x1 x2x2 x3x3 x4x4 MAs(n 8 =sa0):{n 8 =1, n 4 =0, n 3 =1, n 7 =1, n 2 =1, n 6 =1} MAs(n 8 =sa1):{n 8 =0, n 7 =1, n 4 =0, n 2 =1, n 3 =0, n 6 =0, n 10 =0} Substitute nodes: n 6, n 3 17 2011/10/27

18. Substitute node identification  Two MA computations are required for each node  MAs(n t =sa0) and MAs(n t =sa1)  It could identify more than one substitute node MAs(n t =sa0) MAs(n t =sa1) nsnsnsns nsnsnsns 18 2011/10/27

19. Experimental setup  Within ABC [3] environment and on a Linux platform (CentOS 4.6) with a 3.0GHz CPU  Two experiments -Substitute node identification -Circuit size reduction Each benchmark is initially optimized by using resyn2, a local rewriting optimization 19 2011/10/27 [3] Berkeley Logic Synthesis and Verification Group, “ABC: A System for Sequential Synthesis and Verification,” http://www.eecs.berkeley.edu/alanmi/abc/.

20. Substitute node identification CircuitAIG N rep % N sub ratio Time (s) N equ N sub, k>5 i2c1306806.11742.20.21911 pci_spoci.145117011.78905.20.64693 systemcdes31901474.63012.11.56029 spi4053651.6911.43.4142 des_area4857801.61521.95.6516 tv8096094965.238647.817.21462684 systemcaes130542021.53801.917.74815 ac97_ctrl14496980.72421.53.2331 mem_ctrl1564115379.835881.398.81150397 usb_funct158943702.312713.46.310877 aes_core215134522.117423915.229910 pci_bridge32243693091.36212.021.75343 wb_conmax48429560811.6419967.528.218811385 des_perf7928825053.261952.551.456694 average4.53.3 total1211961507271.0195516357 20

21. Circuit size reduction (1/2) CircuitAIG Our approach SAT-based node merging [4] Nr%Time%Time pci_.87877112.190.349.26 i2c9419202.230.143.23 dalu10579619.080.561210 C5315131013010.690.130.72 s9234135313281.850.21.28 C7552141013633.330.443.48 i10185217445.830.861.312 s13207210820612.230.571.817 alu42471190023.116.6322.964 system.264125872.041.34.79 spi342934080.613.761.384 tv80723368954.6714.637.11445 s38417818581240.751.741275 mem_.8815723617.918.6318738 s38584999098241.6614.140.8223 ac97_ctrl10395103740.22.332188 21 [2] S. Plaza, K. H. Chang, I. Markov, and V. Bertacco, “Node Mergers in the Presence of Don’t Cares,” in Proc. Asia South Pacific Design Automation Conf., 2007, pp. 414-419.

22. Circuit size reduction (2/2) CircuitAIG Our approach SAT-based node merging [4] Nr%Time%Time systemc.10585105140.6717.123.8360 usb_f.13320129772.587.151.4681 pci_.17814176950.6714.490.11134 aes_.20509202341.3422.328.61620 b1734523335992.68108.491.65000 wb_.41070391024.7946.986.25000 des_.71327697222.25194.653.75000 average4.495.04 total467.621887 ratio146.81 22

23. Summary  We propose a fast ODC-based node merging algorithm -ATPG-based -3.3 substitute nodes -46.81x faster  We propose a node merging-based approach for circuit size reduction 23 2011/10/27 Yung-Chih Chen, Chun-Yao Wang, "Fast Detection of Node Mergers Using Logic Implications", 2009 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2009), pp. 785-788, Nov. 2009. Yung-Chih Chen, Chun-Yao Wang, "Fast Node Merging with Don’t Cares Using Logic Implications", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1827-1832, Nov. 2010

24. Outline  Introduction  Preliminaries  Node merging with don’t cares  Node addition and removal with don’t cares  Satisfiability-based bounded sequential equivalence checking  Conclusion 24 2011/10/27

25. Node addition and removal  Node addition and removal (NAR) is an extended technique of node merging 25 2011/10/27 A B A B A B C

26. Example: node merging and NAR  And-Inverter Graph (AIG) n1n1 n2n2 n3n3 n4n4 a b c d n5n5 n7n7 n6n6 n 5 and n 6 are functionally non- equivalent Their values only differ when n 2 = 1 and a = c a = c implies n 1 = 0, which blocks n 5 The functional differences of n 5 and n 6 are never observable n 5 can be replaced with n 6 26 2011/10/27

27. Example: node merging and NAR  And-Inverter Graph (AIG) n1n1 n2n2 n3n3 n4n4 a b c d n7n7 n6n6 There is no substitute node that can replace n 6 The added node n 8 can replace n 6 n 2 can be removed as well n8n8 NAR can complement node merging 27 2011/10/27

28. 28 2011/10/27 Problem formulation  Given a target node n t in a circuit, find a node n a which can safely replace n t after it is added into the circuit -n a is named an added substitute node and driven by two nodes existing in the circuit

29. Node addition and removal  Extend our prior node-merging method -sufficient conditions for an added node to be an added substitute node  NAR and node merging both perform node replacement -If an added node n a satisfies Condition 1, it is a substitute node, and thus, an added substitute node n a =1 in MAs(n t =sa0) n a =0 in MAs(n t =sa1) 29 2011/10/27

30. Node addition and removal  We do not iteratively add any one node and then check if it is an added substitute node due to inefficiency 30 2011/10/27 n1n1 n2n2 n3n3 n4n4 a b c d n7n7 n6n6 ? ? ? ? ? ?

31. Node addition and removal  Identify two existing nodes, n f1 and n f2, which are fanin nodes of an added substitute node n a -Suppose n a = AND(n f1, n f2 ) n a =1 in MAs(n t =sa0) n a =0 in MAs(n t =sa1) {n f1 =1, n f2 =1} in MAs(n t =sa0) n f2 =0 in imp({n f1 =1, MAs(n t =sa1)}) nana n f1 n f2 31 2011/10/27

32. 32 2011/10/27 Experimental setup  Within ABC environment and on a Linux platform (CentOS 4.6) with a 3.0GHz CPU  Three experiments -Replaceable node identification -Circuit minimization Each benchmark is initially optimized by using resyn2, a local rewriting optimization

33. Replaceable node identification CircuitAIG Our NM Our NAR N rep % Time (s) N rep % Time (s) i2c1306806.10.252840.40.5 pci_spoci.145117011.70.663043.41.5 systemcdes31901474.61.5135542.52.6 spi4053651.63.495023.46.6 des_area4857801.65.689118.313.3 tv8096094965.217.2341535.541.6 systemcaes130542021.517.7288822.136.8 ac97_ctrl14496980.73.214289.97.5 mem_ctrl1564115379.898.8344322178 usb_funct158943702.36.3343021.616.7 aes_core215134522.115.2807637.539.9 pci_bridge32243693091.321.7370015.247.2 wb_conmax48429560811.628.21349227.9116 des_perf7928825053.251.43437643.482.7 average4.528.8 total271.0590.9 33

34. Average results for totally 23 benchmarks Average results for totally 23 benchmarks Combine our approach with resyn2 Combine our approach with resyn2 Circuit minimization SAT-based NM Our NM Our NAR Reduction % Time (s) Reduction % Time (s) Reduction % Time (s) average5.03.95.0 total21887254.3497.1 ratio 2 44.00.51 (Ours+resyn2) x 3 resyn2 x 6 Ours x 6 Reduction % Time (s) Reduction % Time (s) Reduction % Time (s) average8.64.35.9 total1453.1157.12691.2 34 2011/10/27

35. 35 2011/10/27 Summary  We proposed an ATPG-based NAR approach -No random simulation, no candidates, and no SAT solving -Complement the node-merging approach by finding more replaceable nodes  It has a competitive quality and spends much less CPU time, compared to the SAT-based node-merging approach Yung-Chih Chen, Chun-Yao Wang, "Node Addition and Removal in the Presence of Don’t Cares", 2010 ACM/IEEE Design Automation Conference (DAC2010), pp. 505-510, July 2010. (Best Paper Nominee) Yung-Chih Chen, Chun-Yao Wang, "Logic Restructuring Using Node Addition and Removal", accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)

36. Outline  Introduction  Preliminaries  Node merging with don’t cares  Node addition and removal with don’t cares  Satisfiability-based bounded sequential equivalence checking  Conclusion 36 2011/10/27

37. 37 2011/10/27 SAT-based bounded sequential equivalence checking  SAT-based BSEC F0F0 G0G0 F1F1 G1G1 F n-1 G n-1 FnFn GnGn PIs S0S0 POs... T=0T=1T=n-1T=n

38. 38 2011/10/27  Optimization flow SAT-based bounded sequential equivalence checking MiterUnrolling F0F0 G0G0 PIs POs FFs NM & NAR F’ 0 G’ 0 PIs POs F’ n G’ n PIs POs... NM & NAR SAT solving

39. SAT-based BSEC facilitation CircuitFFsk Original Simplified Speedup SAT T (s) Total T (s) Ratio Saved T (s) b04 132121927.390.123.29585.831924.10 ss_pcm 174471848.372.7855.9933.011792.38 usb_phy196371158.0628.9285.8813.481072.18 sasc 234241967.010.4122.5687.191944.45 des_area 25632312.993.5199.9323.152213.06 i2c 256111739.920.2412.45139.751727.47 simple_spi 2641811183.900.4227.76402.8811156.14 s5378328251038.4037.3485.7312.11952.67 systemcdes 38061412.036.2450.8027.801361.23 s9234422181099.503.1020.0654.811079.44 spi45875242.304500.504651.981.13590.32 b14 490736000.0060.25124.32289.5835875.68 b20980731280.921124.841214.4925.7630066.43 s132071338481150.8319.7297.4511.811053.38 b221470526140.48328.04399.0665.5125741.42 ac97_ctrl 4398141354.900.0115.4287.871339.48 average 116.35 total 103680.966042.706573.58 97107.38 Yung-Chih Chen, Chun-Yao Wang, "Logic Restructuring Using Node Addition and Removal", accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 39

40. Outline  Introduction  Preliminaries  Node merging with don’t cares  Node addition and removal with don’t cares  Satisfiability-based bounded sequential equivalence checking  Conclusion 40 2011/10/27

41. Conclusion  We propose two logic optimization methods -ATPG-based node merging Faster than previous SAT-based methods Competitive quality -ATPG-based node addition and removal Enhance node merging -They can be integrated to facilitate SAT-based BSEC 41 2011/10/27

42. Thank you 42 2011/10/27

43. Node addition and removal  Identify two existing nodes, n f1 and n f2, which are fanin nodes of an added substitute node n a -Suppose n a = AND(n f1, n f2 ) n a =1 in MAs(n t =sa0) n a =0 in MAs(n t =sa1) Condition 2: n f1, n f2 … Condition 3: n f1, n f2 … nana n f1 n f2 43 2011/10/27

44. Condition 2  Condition 2: {n f1 =1, n f2 =1} is in MAs(n t =sa0) nana n f1 n f2 1 1 1 n a =1 in MAs(n t =sa0) n a =0 in MAs(n t =sa1) {n f1 =1, n f2 =1} in MAs(n t =sa0) Condition 3: n f1, n f2 … 44 2011/10/27

45. Condition 3  Condition 3: n f2 =0 is in imp({n f1 =1, MAs(n t =sa1)}) -imp({n f1 =1, MAs(n t =sa1)}) is the set of value assignments logically implied by {n f1 =1, MAs(n t =sa1)} Test set for n t =sa1 n f1 =0 n f1 =1 n a =0 n f2 =0 Condition 3 n a =0 n a =1 in MAs(n t =sa0) n a =0 in MAs(n t =sa1) 45 2011/10/27

46. Condition 3  Condition 3: n f2 =0 is in imp({n f1 =1, MAs(n t =sa1)} ) -imp({n f1 =1, MAs(n t =sa1)}) is the set of value assignments logically implied by {n f1 =1, MAs(n t =sa1)} n a =1 in MAs(n t =sa0) n a =0 in MAs(n t =sa1) {n f1 =1, n f2 =1} in MAs(n t =sa0) n f2 =0 in imp({n f1 =1, MAs(n t =sa1)}) 46 2011/10/27

47. Example  n 6 is a target node to be replaced MAs(n 6 =sa0) n f1 imp({n f1 =1, MAs(n 6 =sa1)}) n1n1 n2n2 n3n3 n4n4 a b c d n7n7 n6n6 n 6 =1, n 2 =1, c=1, b=1, d=1, n 3 =1, n 4 =1 Suppose we select n 3 as n f1 n 6 =0, n 3 =1, c=1, b=1, n 2 =0, d=0, n 4 =0 nana 47 2011/10/27

48. n a identification flow MAs(n t =sa0) imp({n f1 =1, MAs(n t =sa1)}) n a =AND(n f1, n f2 ) Given a target node n t Select n f1 n f2 48 2011/10/27

49. Eight types of n a (1/2) {n f1 =1, n f2 =1} in MAs(n t =sa0) n f2 =0 in imp({n f1 =1, MAs(n t =sa1)}) {n f1 =0, n f2 =1} in MAs(n t =sa0) n f2 =0 in imp({n f1 =0, MAs(n t =sa1)}) {n f1 =1, n f2 =0} in MAs(n t =sa0) n f2 =1 in imp({n f1 =1, MAs(n t =sa1)}) {n f1 =0, n f2 =0} in MAs(n t =sa0) n f2 =1 in imp({n f1 =0, MAs(n t =sa1)}) nana n f1 n f2 nana n f1 n f2 nana n f1 n f2 nana n f1 n f2 49 2011/10/27

50. Eight types of n a (2/2) {n f1 =1, n f2 =1} in MAs(n t =sa1) n f2 =0 in imp({n f1 =1, MAs(n t =sa0)}) {n f1 =0, n f2 =1} in MAs(n t =sa1) n f2 =0 in imp({n f1 =0, MAs(n t =sa0)}) {n f1 =1, n f2 =0} in MAs(n t =sa1) n f2 =1 in imp({n f1 =1, MAs(n t =sa0)}) {n f1 =0, n f2 =0} in MAs(n t =sa1) n f2 =1 in imp({n f1 =0, MAs(n t =sa0)}) nana n f1 n f2 nana n f1 n f2 nana n f1 n f2 nana n f1 n f2 50 2011/10/27

51. Circuit size reduction For each node n t Identify substitute nodes and replace n t Identify added substitute nodes and replace n t n t is replaced n t has a fanin driving only n t 51 2011/10/27