1. Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania 18042 nestorj@lafayette.edu ECE 425 - VLSI Circuit Design Lecture 18 - Verilog Part 2 Spring 2007

2. ECE 425 Spring 2005Lecture 18 - Verilog Part 22 Announcements  Reading  Book: 5.1-5.4  Verilog Handout: Section 5

3. ECE 425 Spring 2005Lecture 18 - Verilog Part 23 Where we are  Last Time:  Sequential Logic  Today:  Sequential Logic in Verilog  Finite State Machines in Verilog

4. ECE 425 Spring 2005Lecture 18 - Verilog Part 24 Outline - More about Verilog  A Little More about Combinational Logic   A Quick Review  Parameterized modules  Symbolic Constants  Sequential Logic  Basic Constructs  Synchronous & Asynchronous Reset  Mixing Combinational & Registered Logic  Examples  Finite State Machines

5. ECE 425 Spring 2005Lecture 18 - Verilog Part 25 Review - Verilog Module Declaration  Describes the external interface of a single module  Name  Ports - inputs and outputs  General Syntax: module modulename ( port1, port2,... ); port1 direction declaration; port2 direction declaration; reg declarations; module body - “parallel” statements endmodule // note no semicolon (;) here!

6. ECE 425 Spring 2005Lecture 18 - Verilog Part 26 Parameterized Modules  Parameters - define values that can change  Declaration: module mod1(in1, in2, out1, out2); parameter N=default-value; input [N-1 : 0] in1, in2; output [N-1 : 0] out1; … endmodule  Instantiation: wire [7:0] w, x, y; wire z; mod1 #(8) my_mod1(w,x,y,z); Defines Parameter N Uses Parameter NSets Parameter N for instance my_mod1 Sizes must match instantiated value!

7. ECE 425 Spring 2005Lecture 18 - Verilog Part 27 Parameterized Modules: Example  N-bit 2-1 multiplexer (parameterized bitwidth) module mux2( sel, a, b, y ); parameter bitwidth=32; input sel; input [bitwidth-1:0] a, b; output [bitwidth-1:0] y; assign y = sel ? b : a; endmodule  Instantiations mux2 #(16) my16bit_mux(s, a,b, c); mux2 #(5) my5bit_mux(s, d, e, f); mux2 #(32) my32bit_mux(s, g, h, i); mux2 myDefault32bit_mux(s, j, k, l); Defines Parameter bitwidth (default value: 32 ) Uses Parameter bitwidth to set input, output size 16-bit mux 5-bit mux 32-bit mux 32-bit mux (default)

8. ECE 425 Spring 2005Lecture 18 - Verilog Part 28 Symbolic Constants with Parameters  Idea: use parameter to name “special constants” parameter RED_ALERT = 2’b11; parameter YELLOW_ALERT = 2’b01; parameter GREEN_ALERT = 2’b00;  Don’t change in module instances  Do this to make your code more understandable  For others reading your code  For yourself reading your code after some time has passed

9. ECE 425 Spring 2005Lecture 18 - Verilog Part 29 Symbolic Constant Example  7-segment decoder from Verilog Handout (Part 1) module seven_seg_display_decoder(data, segments); input[3:0]data; output[6:0]segments; reg[6:0]segments; // Segment # abc_defg hex equivalent parameterBLANK= 7’b111_1111;// h7F parameterZERO= 7’b000_0001;// h01 parameterONE = 7’b100_1111;// h4F parameterTWO= 7’b001_0010;// h12 parameterTHREE= 7’b000_0110;// h06 parameterFOUR= 7’b100_1100;// h4C parameterFIVE= 7’b010_0100;// h24 parameterSIX= 7’b010_0000;// h20 parameterSEVEN= 7’b000_1111;// h0F parameterEIGHT= 7’b000_0000;// h00 parameterNINE= 7’b000_0100;// h04

10. ECE 425 Spring 2005Lecture 18 - Verilog Part 210 Symbolic Constant Example  7-segment decoder from Verilog handout Part 2) always @(data) case (data) 0: segments = ZERO; 1: segments = ONE; 2: segments = TWO; 3: segments = THREE; 4: segments = FOUR; 5: segments = FIVE; 6: segments = SIX; 7: segments = SEVEN; 8: segments = EIGHT; 9: segments = NINE; default: segments = BLANK; endcase endmodule

11. ECE 425 Spring 2005Lecture 18 - Verilog Part 211 Symbolic Constants using `define  Like C/C++, Verilog has a preprocessor  `define - equivalent to #define in C/C++  Symbolic constant definition: `define ZERO 7’b0000_0001  Symbolic constant usage: preface with “`” segments = `ZERO;  Other preprocessor directives  `ifdef  `else  `endif Used for conditional compilation

12. ECE 425 Spring 2005Lecture 18 - Verilog Part 212 Outline - More about Verilog  A Little More about Combinational Logic  A Quick Review  Parameterized modules  Symbolic Constants  Sequential Logic   Basic Constructs  Synchronous & Asynchronous Reset  Mixing Combinational & Registered Logic  Examples  Discuss Lab 9

13. ECE 425 Spring 2005Lecture 18 - Verilog Part 213 Sequential Design in Verilog - Basic Constructs  Describe edge-triggered behavior using:  always block with“edge event” always @(posedge clock-signal) always @(negedge clock-signal)  Nonblocking assignments ( <= ) @always(posedge clock-signal) begin output1 <= expression1;... output2 <= expression2;... end Registered Outputs for positive edge-trigger for negative edge-trigger Non-Blocking Assignments (deferred update)

14. ECE 425 Spring 2005Lecture 18 - Verilog Part 214 Simple Examples: Flip-Flop, Register module flipflop(d, clk, q); input d; input clk; output q; reg q; always @(posedge clk) q <= d; endmodule module flop3(clk, d, q); input clk; input[3:0] d; output [3:0] q; reg[3:0] q; always @(posedge clk) q <= d; endmodule D CLK QD Q 44

15. ECE 425 Spring 2005Lecture 18 - Verilog Part 215 Simple Example: Register with Reset  Synchronous - resets on clock edge if reset=1 module flopr(clk, reset, d, q); input clk; inputreset; input[3:0]d; output [3:0]q; reg[3:0] q; always @(posedge clk) if (reset) q <= 4’b0; else q <= d; endmodule D CLK Q 44 RESET

16. ECE 425 Spring 2005Lecture 18 - Verilog Part 216 Simple Example: Register with Reset  Asynchronous - resets immediately if reset=1 module flopr(clk, reset, d, q); input clk; inputreset; input[3:0]d; output [3:0]q; reg[3:0] q; always @(posedge clk or posedge reset) if (reset) q <= 4’b0; else q <= d; endmodule D CLK Q 44 RESET

17. ECE 425 Spring 2005Lecture 18 - Verilog Part 217 Another Example: Shift Register module shiftreg(clk, sin, q); input clk; inputsin; output [3:0]q; reg[3:0] q; always @(posedge clk) begin q[3] <= q[2]; q[2] <= q[1]; q[1] <= q[0]; q[0] <= sin; end endmodule Non-Blocking Assignments (update values after clock edge!)

18. ECE 425 Spring 2005Lecture 18 - Verilog Part 218 Another Example: 4-bit Counter  Basic Circuit: module counter(clk, Q); input clk; output [3:0] Q; reg [3:0] Q; // a signal that is assigned a value always @( posedge clk ) begin Q <= Q + 1; end endmodule  Questions: How about carry?  Putting carry in this code would “register” carry  Result: carry delayed one clock cycle  Need to mix sequential & combinational logic carry <= (Q == 4’b1111); // WRONG!

19. ECE 425 Spring 2005Lecture 18 - Verilog Part 219 always@(posedge clock) always @(inputlist) or assign Combining Sequential and Combinational Outputs  General circuit - both registered and comb. outputs  Approach: multiple always blocks

20. ECE 425 Spring 2005Lecture 18 - Verilog Part 220 Registered Output Combinational Output Example: Adding carry to 4-bit Counter module counter(clk, Q, carry); input clk; output [3:0] Q; output carry; reg [3:0] Q; // a signal that is assigned a value assign carry = (Q == 4'b1111); always @( posedge clk ) begin Q <= Q + 1; end endmodule

21. ECE 425 Spring 2005Lecture 18 - Verilog Part 221 Refining the Counter: Synchronous Clear module counter(clk, clr, Q, carry); input clk, clr; output [3:0] Q; output carry; reg [3:0] Q; // a signal that is assigned a value assign carry = (Q == 4'b1111); always @( posedge clk ) begin if (clr) Q <= 4'd0; else Q <= Q + 1; end endmodule Q changes on clk edge (usually preferred)

22. ECE 425 Spring 2005Lecture 18 - Verilog Part 222 Refining the Counter: Asynchronous Clear module counter(clk, clr, Q, carry); input clk, clr; output [3:0] Q; output carry; reg [3:0] Q; // a signal that is assigned a value assign carry = (Q == 4'b1111); always @( posedge clr or posedge clk ) begin if (clr) Q <= 4'd0; else Q <= Q + 1; end endmodule Q changes on clk edge OR on reset

23. ECE 425 Spring 2005Lecture 18 - Verilog Part 223 Lab 8 - Comb. Design with Verilog  Prelab: write out case statement by hand for binary decoder  In the lab:  Type in and simulate binary decoder using Verilogger or Modelsim  FTP to Linux & synthesize using Synopsys tools  FTP to Suns & convert optimized logic to layout  FTP back from Suns & examine layout

24. ECE 425 Spring 2005Lecture 18 - Verilog Part 224 Lab 8 - Decoder Design in Verilog  Part 1: design, simulate, and synthesize a decoder module dec2_4(d_in, d_out); input [1:0] d_in; output [3:0] d_out; reg [3:0] d_out; always @(d_in) begin case (d_in) 2’b00 : d_out = 4’b0001; … default: d_out = 4’bxxxx; endcase end endmodule d_in d_out Fill in the 4 cases with the proper values

25. ECE 425 Spring 2005Lecture 18 - Verilog Part 225 Lab 8 - Decoder Design in Verilog  Part 2: add an inverted output to your decoder module dec2_4(d_in, d_out, d_out_b); input [1:0] d_in; output [3:0] d_out, d_out_b; reg [3:0] d_out, d_out_b; always @(d_in) begin case (d_in) 2’b00 : d_out = 4’b0001; … default: d_out = 4’bxxxx; endcase end endmodule Add code to generate d_out_b d_in d_out d_out_b

26. ECE 425 Spring 2005Lecture 18 - Verilog Part 226 Lab 8 - Additional Tasks  Modify decoder to intentionally create a “latch inference” and synthesize  Create, simulate, and synthesize designs for:  Row decoder for D/A converter (include d2 input and complemented outputs) - compare to your hand layout  4-bit incrementer  4-bit adder

27. ECE 425 Spring 2005Lecture 18 - Verilog Part 227 Lab 9 Part 1: Extend the Counter  Add synchronous input “updown”  Count up when updown == 1  Count down when updown == 0  Add synchronous load, data input  Load counter with 4-bit data when load == 1  Normal counting when load == 0  Simulate using Verilogger  Synthesize with Synopsys Tools (and plot schematic)  Generate layout with db2mag & note cell area  Extract counter & simulate with irsim

28. ECE 425 Spring 2005Lecture 18 - Verilog Part 228 Lab 9 Part 2: 8-bit Shift Register  Code shift register shown below and repeat previous steps to simulate and synthesize.  10% Extra credit: parameterize shift register for arbitrary number of bits N and synthesize for N=12.

29. ECE 425 Spring 2005Lecture 18 - Verilog Part 229 Outline - More about Verilog  A Little More about Combinational Logic  A Quick Review  Parameterized modules  Symbolic Constants  Sequential Logic  Basic Constructs  Synchronous & Asynchronous Reset  Mixing Combinational & Registered Logic  Examples  Finite State Machines

30. ECE 425 Spring 2005Lecture 18 - Verilog Part 230 Review - Finite State Machines  Defined in terms of  State Register - n flip-flops  State - one of up to 2 n values  Transitions - conditions for state changes on active edge of clock  Common Representations  State Transition Diagrams  State Transition Tables

31. ECE 425 Spring 2005Lecture 18 - Verilog Part 231 Review - State Transition Diagrams  "Bubbles" - states  Arrows - transition edges labeled with condition expressions  Example: Car Alarm arm door honk clk f clk = 1Hz

32. ECE 425 Spring 2005Lecture 18 - Verilog Part 232 Review - State Transition Table  Transition List - lists edges in STD PSConditionNSOutput IDLEARM' + DOOR'IDLE0 IDLEARM*DOORBEEP0 BEEPARMWAIT1 BEEPARM'IDLE1 WAITARMBEEP0 WAITARM'IDLE0

33. ECE 425 Spring 2005Lecture 18 - Verilog Part 233 State Machine Design  Traditional Approach:  Create State Diagram  Create State Transition Table  Assign State Codes  Write Excitation Equations & Minimize  HDL-Based State Machine Design  Create State Diagram (optional)  Write HDL description of state machine  Synthesize

34. ECE 425 Spring 2005Lecture 18 - Verilog Part 234 Coding FSMs in Verilog - “Explicit” Style  Clocked always block - state register  Combinational always block -  next state logic  output logic

35. ECE 425 Spring 2005Lecture 18 - Verilog Part 235 Coding FSMs in Verilog - Code Skeleton  Part 1 - Declarations module fsm(inputs, outputs); input...; reg...; parameter [NBITS-1:0] S0 = 2'b00; S1 = 2'b01; S2 = 2b'10; S3 = 2b'11; reg [NBITS-1 :0] CURRENT_STATE; reg [NBITS-1 :0] NEXT_STATE; State Codes State Variable

36. ECE 425 Spring 2005Lecture 18 - Verilog Part 236 Coding FSMs in Verilog - Code Skeleton  Part 2 - State Register, Logic Specification always @(posedge clk) begin CURRENT_STATE <= NEXT_STATE; end always @(CURRENT_STATE or xin) begin case (CURRENT_STATE) S0:... determine NEXT_STATE, outputs S1 :... determine NEXT_STATE, outputs end case end // always endmodule

37. ECE 425 Spring 2005Lecture 18 - Verilog Part 237 FSM Example - Car Alarm  Part 1 - Declarations, State Register module car_alarm (arm, door, reset, clk, honk ); input arm, door, reset, clk; output honk; reg honk; parameter IDLE=0,BEEP=1,HWAIT=2; reg [1:0] current_state, next_state; always @(posedge reset or posedge clk) if (reset) current_state <= IDLE; else current_state <= next_state;

38. ECE 425 Spring 2005Lecture 18 - Verilog Part 238 FSM Example - Car Alarm  Part 2 - Logic Specification always @(current_state or arm or door) case (current_state) IDLE : begin honk = 0; if (arm && door) next_state = BEEP; else next_state = IDLE; end BEEP: begin honk = 1; if (arm) next_state = HWAIT; else next_state = IDLE; end

39. ECE 425 Spring 2005Lecture 18 - Verilog Part 239 FSM Example - Car Alarm  Part 3 - Logic Specification (cont’d) HWAIT : begin honk = 0; if (arm) next_state = BEEP; else next_state = IDLE; end default : begin honk = 0; next_state = IDLE; end endcase endmodule

40. ECE 425 Spring 2005Lecture 18 - Verilog Part 240 FSM Example - Verilog Handout  Divide-by-Three Counter S0 out=0 S1 out=0 S1 out=1 reset

41. ECE 425 Spring 2005Lecture 18 - Verilog Part 241 Verilog Code - Divide by Three Counter Part 1 module divideby3FSM(clk, reset, out); inputclk; inputreset; outputout; reg[1:0] state; reg[1:0]nextstate; parameterS0 = 2’b00; parameterS1 = 2’b01; parameterS2 = 2’b10; // State Register always @(posedge clk or posedge reset) if (reset) state <= S0; else state <= nextstate;

42. ECE 425 Spring 2005Lecture 18 - Verilog Part 242 Verilog Code - Divide by Three Counter Part 2 // Next State Logic always @(state) case (state) S0: nextstate = S1; S1: nextstate = S2; S2: nextstate = S0; default: nextstate = S0; endcase // Output Logic assign out = (state == S2); endmodule

43. ECE 425 Spring 2005Lecture 18 - Verilog Part 243 Example from Book: “01 Recognizer”  See Example 5-3, p. 285  Output 1 when input=0 for 1 clock cycle, then 1 bit1bit2 input=0 / output=0 0 / 0 1 / 1 1 / 0 input output clk

44. ECE 425 Spring 2005Lecture 18 - Verilog Part 244 Verilog Code - 01 Recognizer Part 1 module recognizer (clk, reset, rin, rout); input clk, reset, rin; output rout; reg rout; parameter [1:0] bit1=2'b00, bit2=2'b01; reg [1:0] current_state, next_state; always @(posedge clk) if (reset) current_state = bit1; else current_state <= next_state; always @(current_state or rin) case (current_state) bit1: begin rout = 1'b0; if (rin == 0) next_state = bit2; else next_state = bit1; end

45. ECE 425 Spring 2005Lecture 18 - Verilog Part 245 Verilog Code - 01 Recognizer Part 1 bit2: begin if (rin == 1'b0) begin rout = 1'b0; next_state = bit2; end else begin rout = 1'b1; next_state = bit1; end default: begin rout = 1'b0; next_state = bit1; end endcase endmodule

46. ECE 425 Spring 2005Lecture 18 - Verilog Part 246 Verilogger Demo: Simulate Recognizer  Download from http://foghorn.cadlab.lafayette.edu/ece425/examples/recognizer.v  Add to project manager and simulate  Note that it’s a Mealy machine (output changes when input changes)

47. ECE 425 Spring 2005Lecture 18 - Verilog Part 247 Lab 10 - Extend and Synthesize Recognizer  Extend to recognize the string “0110”  Adapt to use negative edge-triggered clock  Synthesize using script: “ compile_design.scr ”  cp /home/cad/compile_design.scr  Change file / module names in compile_design.scr  dc_shell -f compile_design.scr  View & plot logic design with design_analyzer  Synthesize, plot magic file, and note area

48. ECE 425 Spring 2005Lecture 18 - Verilog Part 248 Coming Up  Sequential Logic Timing  Chip-Level Design  Project Assignment