1. Designed by Mikael Collin, June 2001 Dynamic Arbitration through OS Controlled Processor Priority ” Reducing Occurrences of Priority Inversion in MSoC’s Using Dynamic Processor Priority Assignment” 1 3 1456 269 0713 Task queue cpu1 Task queue cpu2 Task queue cpu3 2 Processor Priority Registers Processor Priority Executing task Ready,waiting, Task owning resource Task requesting resource Arbitration bus Priority bus Requests Grants HL LowHigh HL LowHigh Static processor priorityDynamic processor priority priority inversion Real-Time Unit (RTU)  Functionality Centralised real-time scheduler in hardware Handles generic number of tasks and priorities Supports up to three processors (today) Microsecond granularity Total view of the system state (at any instant)  Augmentations Processor Priority Assignment unit Performs mapping of relative task priorities to absolute processor priorities Provides the arbiter with processor priorities via priority bus Arbitration Unit  F unctionality Centralised priority based arbitration unit Arbitrates generic number of processors Uses arbitrary fairness mechanism  Augmentations Processor priority registers to store current processor priorities www.mrtc.mdh.se/socrates Local Blocking Interprocessor Blocking Shared ResourceImplicit Bus-Blocking Bus request Bus grant or blocked tasks Assignment unit System-on-a-Chip Freedom The augmentations to both RTU and arbitration unit along with the added priority bus relies on the type of design freedom possible in System- On-a-Chip(SoC) designs. SoC designs can easily add new internal buses in comparison to board based systems with standard components. Priority inversion and blocking in single-processor real-time systems are known problems and there exist solutions to handle them. The same problem in multi-processor real-time systems becomes more complex due to interprocessor blocking, which can generate system-level priority inversion scenarios. Implicit blocking is another type of blocking that occurs on a shared bus when several nodes request the bus simultaneously and all requesting tasks become blocked by the new bus master. This type of blocking due to poor arbitration algorithms or static processor priority assignment results in priority inversion and an increase of a task´s response time. To reduce the number of occurrences of priority inversion due to implicit blocking a non-standard solution using System-On-a-Chip freedom is proposed where priorities of the processors are controlled by the operating system, in this case a hardware scheduling unit (RTU). The processors priority assigned by the hardware scheduler are shared with the arbitration unit via an added priority bus. Priorities of all currently executing tasks are mapped to processor priority in a one-to-one mapping which makes the priority assignment and the arbitration dynamic. In a system with static processor priority, a high priority processor executing a (from the system point of view) low priority task can block a high priority task on the bus. A priority inversion situation will never occur in a system utilising dynamic processor priorities, where processor priorities reflects the relative priorities of the currently executing tasks on each processor.  Formalisation To prove the effectiveness of the solution, a tasks response time need to be formalised with a model that accounts for all possible types of blocking in a multiprocessor system.  Simulator In order to verify the correctness of our ideas and model, a simulator is being developed called MP-rmsim (Multi- Processor Rate Monotonic simulator). The simulator will simulate the complete system taking arbitration and bus access time into account. The Future... Classifications of blocking in multiprocessor systems System bus