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1/1/ / faculty of Electrical Engineering eindhoven university of technology Processor support devices Part 1:Interrupts and shared memory dr.ir. A.C. Verschueren.

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Presentation on theme: "1/1/ / faculty of Electrical Engineering eindhoven university of technology Processor support devices Part 1:Interrupts and shared memory dr.ir. A.C. Verschueren."— Presentation transcript:

1 1/1/ / faculty of Electrical Engineering eindhoven university of technology Processor support devices Part 1:Interrupts and shared memory dr.ir. A.C. Verschueren Eindhoven University of Technology Section of Digital Information Systems

2 1/1/ / faculty of Electrical Engineering eindhoven university of technology What are 'processor support devices'? Processor support devices extend the functionality of the processor core –This includes almost everything in a computer except the input/output control logic –Can add exactly the needed amount of functionality –But ends up with a lot of separate hardware parts –Which must be interconnected, slowing down the system

3 1/1/ / faculty of Electrical Engineering eindhoven university of technology Integrate processor support with CPU Good example: –Intel 80486: 32 bits CPU, memory management (segmenting & paging), floating point co-processor, 'caches' Not so good example: –Philips 68070: 32 bits CPU, DMA and interrupt controllers, timers, standard and I 2 C serial input/output I/O is NOT ‘processor support’

4 1/1/ / faculty of Electrical Engineering eindhoven university of technology interrupt requests Interrupt handling The number of interrupts varies a lot (0.. >200) –Use separate interrupt controller devices to accomodate interrupt request receiver mask register & logic priority & selection logic vector generator vector request & vector transfer CPU interface 'interrupt handled’ enable / disable mode setting s vector setting s (I/O ports) ‘in service register’: routine started but not finished yet ‘interrupt request register’: requested but not started yet

5 1/1/ / faculty of Electrical Engineering eindhoven university of technology Equally important interrupts Giving these fixed priorities leads to 'starvation' –The lowest priority never gets handled (or very slow) Solution: use 'rotating priority' within such a group lowest priority! interrupt 4 handled priority

6 1/1/ / faculty of Electrical Engineering eindhoven university of technology ‘Cascading’ to get more interrupt inputs master controller interrupt request vector handshake vector interrupt interrupt inputs slave controller 1 slave controller N slave selection for vector generation Master should not disable slave input during interrupt Limited capabilities for rotating priorities only within slaves !

7 1/1/ / faculty of Electrical Engineering eindhoven university of technology ‘Daisy chaining’ to get more interrupts Very slow: signals must pass through all controllers Inflexible: priority determined by placement in chain interrupt vector interrupt request controller 1 controller N interrupt inputs in out in out 'false' vector handshake No request: out  in Active request: out  ‘true’ Give vector if: out AND (NOT in)

8 1/1/ / faculty of Electrical Engineering eindhoven university of technology The end of an interrupt routine Controllers need to know when a routine ends –To allow the next interrupt on the same input –To restore interrupt masks to their original status –To modify priorities in a rotating priority group This event is completely determined by software! –Use special RET instruction, 'visible' to controllers –Inform the interrupt controllers with I/O operations

9 1/1/ / faculty of Electrical Engineering eindhoven university of technology I/O deviceCPU Shared memory Direct Memory Access allows both the CPU and I/O devices access to the same main memory –The fastest solution: multi-ported shared memory read write addr data read write addr data (2-ported) memory CPU and I/O memory accesses do not interfere  Real 2-port memory is very expensive, 3 ports and up is not available!

10 1/1/ / faculty of Electrical Engineering eindhoven university of technology Shared memory with an arbiter Multi ported memory may be simulated with an ‘arbiter’ and a higher speed (normal) memory CPU read write addr data I/O device read write addr data memory arbiter fast(er) memory wait True simultaneous access is impossible! Fast memory is expensive ! May have to wait !

11 1/1/ / faculty of Electrical Engineering eindhoven university of technology Combine shared and private memory  Communication confined to a small memory area CPU works mostly in private memory: using an arbiter does not degrade performance! I/O device read write addr data shared memory private memory CPU read write addr data select address decoder I/O device read write addr data shared memory selec t Simple to have more devices

12 1/1/ / faculty of Electrical Engineering eindhoven university of technology system bus input/ output module global memory module I/O proc. + memory + I/O ports Modular systems Access to the system bus and shared memories requires arbitration ( = ‘data traffic control’) main proc. + memory arbiter ? ! ? ? ! !

13 1/1/ / faculty of Electrical Engineering eindhoven university of technology I/O processo r Main processo r global memory module I/O proc. + memory + I/O ports main proc. + memory arbiter Local memory 2 3 Global memory 3 2 Shared local memory 2 Memory mapping Mapping done by address decoding hardware –Which can place memories at different addresses ! Shared local memories require complex arbiters

14 1/1/ / faculty of Electrical Engineering eindhoven university of technology ‘Standard’ system buses Standardisation needed for ‘plug and play’ A lot of them exist (Multibus, VME, EISA....) –Multibus designed by Intel for 80x86 series –VME bus designed by Motorola for 680x0 series They compete for the most complex protocols  Bus signals optimised for one processor (series) –Using an Intel processor on a VME bus is not simple

15 1/1/ / faculty of Electrical Engineering eindhoven university of technology Shared bus Direct Memory Access –A protocol must be used to transfer bus mastership –Slower than shared memory solutions –I/O hardware must create all processor bus lines ! CPU Memory request grant CPU has bus I/O HW DMArequest DMAgrant read write data address CPU releases I/O HW has bus CPU takes bus back

16 1/1/ / faculty of Electrical Engineering eindhoven university of technology Memory Using a separate DMA controller DMA controller can handle multiple I/O requests –Requires the same functionality as multiple interrupts (masking, priorities...) CPU I/O DMA control in out read write address DMArequest DMAgrant IOrequest IOreq in out read write data address in out data read write data address Simple interface !

17 1/1/ / faculty of Electrical Engineering eindhoven university of technology Types of DMA controllers (1) Direct processor controlled DMA (generation 1) –Transfers one data block at a time –Requires main processor support for each data block Instruction list controlled DMA (generation 2) –Transfers multiple data blocks autonomously –Controlled by command (linked) list in memory

18 1/1/ / faculty of Electrical Engineering eindhoven university of technology Types of DMA controllers (2) DMA co-processors (generation 3) –Handle I/O tasks including transfer of data blocks –Run their own programs (stored in DMA memory), controlled by 'messages' in main memory main processor DMA co-processor I/O hardware main memory DMA memory


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