1 Presenter: Chien-Chih Chen. 2 An Assertion Library for On- Chip White-Box Verification at Run-Time On-Chip Verification of NoCs Using Assertion Processors.
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2 An Assertion Library for On- Chip White-Box Verification at Run-Time On-Chip Verification of NoCs Using Assertion Processors The Chip is Ready. Am I done? On-chip Veriﬁcation using Assertion Processors Exception Handling in Microprocessors Using Assertion Libraries
In complex System-on-a-Chip (SoC) designs, designers often need to add new features into an original processor core, such as to extend the exception handling mechanism to consider exceptions in the remaining portion of the SoC design. We present in this paper a scalable architecture that can be used to add complex exception handling mechanisms in processor cores and how it can be used to extend the fixed set of exceptions found in microprocessor cores. This mechanism is based on the use of assertion libraries linked by an assertion processor to incorporate these new functionalities. 3
To observe designed bugs is difficult in complex original microprocessor designs. It is inefficient to design exception handling for each module in microprocessor if there are no original designers support. 4
Scan the assertion chain to detect which assertion has cause failure. Encode the possible tasks that must be performed for each assertion. Perform specific tasks to overcome the error or exception condition. 7
8 Scan Detection if (error detected) begin count = count + 1; if (esci == 1) ErrorNo = count; Priority Encoding from ErrorNo Error Correction case (ErrorPriority) Halt IC HW Reset SW Interrupt Exception Handling HW
10 SPM is popular for real-time embedded systems. Whereas caches use a MMU to control data accesses, but SPM directly maps certain addresses to the SRAM. SPM is that it avoids the cache’s costly MMU. SPM is 100% statically predictable, whereas the variables stored in the cache depend upon the dynamic execution history.
Decrease hardware operational frequency. Change basic node functionality. Put core into idle or sleep mode. 14 M H L
Assertion be a powerful tool to capture design errors in complex design. The extended exception handling mechanism turned IP design into a flexible structure, incorporating low overhead into original core design. 15
The concept of assertion processor and OVL. one useful mechanism to monitor microprocessor internal cycle by cycle behaviors. To detect CPU illegal behaviors by setting test expression corresponding to software function. 16