1. Interprocessor arbitration
Arbitration logic resolves bus conflict
It would be the part of system bus controller
Two types:
Serial arbitration procedure
Parallel arbitration procedure
Arbitration procedures services all processor requests on the basis of established priorities

2. Serial arbitration procedure

3. Parallel arbitration logic

4. Dynamic arbitration algorithms
Time slice
Polling
The LRU
FIFO
Rotating daisy chain

5. Interprocessor communication and synchronization
Shared memory:
Communication is by common area of shared memory
Sender alert the receiver by interrupt and data transfer through I/O path.

6. Loosely coupled :
Communication is through I/O channels
One calls a procedure which resides in the memory of the destination
O.S. in each node controls the communocation

7. Interprocessor synchrinization
Special case of communication where the information transferred is control signals
Needed to enforce the correct sequence of processes and to ensure mutually exclusive access to shared writable data.

8. Multiprocessor systems usually include a no
Multiprocessor systems usually include a no. of mechanisms to deal with the synchronization of resources
One of the most popular methods is through the use of a binary semaphore

9. Mutual exclusion with a semaphore
A properly functioning multiprocessor system must provide a mechanism that will guarantee orderly access to shared memory and other shared resources
This is necessary to protect data from being changed simultaneously by two or more processors
This mechanism has been termed mutual exclusion
Mutual exclusion enables one processor to exclude or lockout access to a shared resources by other processors when it is in a critical section

10. A critical section is a program sequence, that once begun, must complete execution before another processor accesses to same shared resources
A binary variable called semaphore is often used to indicate whether or not a processor is executing a critical section
It is a s/w controlled flag that is stored in a memory location that all processors can access. When the semaphore is equal to 1, it means that a processor is executing a critical program, so that the shared memory is not available to other processors

11. When the semaphore is equal to 0, the shared memory is available to any requesting processor.
If a processor accesses shared memory and is executing a critical section it sets the semaphore and clears it when it is finished
Testing and setting the semaphore is itself a critical section. If it is not two or more may set the semaphore simultaneously, allowing them to enter critical section at the same time.
A semaphore can be initialized by means of a test and set instruction in conjunction with a hardware lock mechanism.

12. A hardware lock is a processor generated signal that serves to prevent other processors from using the system bus as long as the signal is active
The test and set instruction tests and sets a semaphore and activates a lock mechanism during the time that instruction is being executed. This prevents other processors from changing the semaphore between the time that the processor is testing it and the time that it is setting it.
Assume that the semaphore is a memory location symbolized by SEM

13. Let the mnemonic TSL designate “the test and set while locked” operation. The instruction
TSL SEM performs
R  M[SEM] test semaphore
M[SEM]  1 set semaphore
The value in R determines what to do next
The last instruction in the program must clear SEM to 0

14. Cache coherence Conditions for incoherence:
A memory scheme is coherent if the value returned on a load instruction is always the value given by the latest store instruction with the same address
Conditions for incoherence:
cache coherence problems exist in multiprocessors with private caches because of the need to store writable data
Consider the 3 processor configuration with private caches as shown below

18. Solutions to the cache coherence problems:
Another configuration that may cause consistency is a DMA activity
Solutions to the cache coherence problems:
Disallow private caches for each processor and have a shared cache memory associated with main memory
Only nonshared and read only data to be stored in caches. – cachable
shared writable data -- non cachable
Compiler must tag data as cachable or non cachable and the system h/w makes sure that only cachable

19. data are stored in caches and non cachable data remain in main memory.
Centralized global table in its compiler
Hardware solutions:
Snoopy cache controller– monitor all bus requests
All caches constantly monitor the bus for possible write operations
Write through policy.