1. 3/30/05Agrawal: Implication Graphs1 Implication Graphs and Logic Testing Vishwani D. Agrawal James J. Danaher Professor Dept. of ECE, Auburn University Auburn, AL 36849 vagrawal@eng.auburn.edu www.eng.auburn.edu/~vagrawal Joint research with:M. L. Bushnell, Rutgers University, Piscataway, NJ K. K. Dave, ATI Research, Yardley, PA

2. 3/30/05Agrawal: Implication Graphs2 Implication Graph An implication graph (IG) represents the implication relations between pairs of Boolean variables. a ab b an implication contrapositive implication

3. 3/30/05Agrawal: Implication Graphs3 Implication Graph of a Logic Gate a b c c = ab Boolean false function: ab c = 0 ac + bc + abc = 0 Chakradhar et al. -- IEEE-D&T, 1990 a b c c b a

4. 3/30/05Agrawal: Implication Graphs4 Global Implications and Transitive Closure a b c a b c c b a Transitive closure edge c ≡ 0

5. 3/30/05Agrawal: Implication Graphs5 Transitive Closure Transitive closure (TC) of a directed graph contains the same set of nodes as the original graph. If there is a directed path from node a to b, then the transitive closure contains an edge from a to b. A graph b c d a b c d a A GraphTransitive Closure a b c d a 0 1 0 0 b 0 0 1 0 c 0 0 0 1 d 0 0 0 0 a b c d a 0 1 1 1 b 0 0 1 1 c 0 0 0 1 d 0 0 0 0

6. 3/30/05Agrawal: Implication Graphs6 Transitive Closure: Warshall’s Algorithm procedure Warshall (var A : array[1…n, 1…n] of boolean; C : array[1…n, 1…n] of boolean); { Warshall makes A the transitive closure of C } var i, j, k : integer; begin for i := 1 to n do for j := 1 to n do A[i, j] := C[i, j]; for k := 1 to n do O(n 3 ) for i := 1 to n do for j := 1 to n do if A[i, j] = false then A[i, j] := A[i, k] and A[k, j] end; { Warshall } S. Warshall, “A Theorem on Boolean Matrices,” J. ACM, vol. 9, no. 1, pp. 11-12, 1962. A. V. Aho, J. E. Hopcroft and J. D. Ullman, Data Structures and Algorithms, Reading, Massachusetts: Addison-Wesley, 1983, p. 213.

7. 3/30/05Agrawal: Implication Graphs7 Transitive Closure: Update Algorithm Start constructing transitive closure (TC) by placing all nodes and no edges. This edge-less graph is its own TC. Add edges to TC in any arbitrary order  For each edge i → j find P : set of parent nodes of i C : set of child nodes of j  Add edges {P, i } → {C, j } K. Dave, “Using Contrapositive Rule to Enhance the Implication Graphs of Logic Circuits,” Master’s Thesis, Rutgers University, Dept. of ECE, Piscataway, New Jersey, May 2004.

8. 3/30/05Agrawal: Implication Graphs8 Update Algorithm i j p2 p1 c1 {P, i } {C, j } Edges before i→ j is added Edges after i→ j is added

9. 3/30/05Agrawal: Implication Graphs9 Update Algorithm Example b c d a b c d a b c d a b c d a b c d a b c d a A directed graph Transitive closure

10. 3/30/05Agrawal: Implication Graphs10 Logic Testing: Stuck-at Fault A type of fault, which causes a line to hold a constant logic value, irrespective of change of state at previous stages. There are two types of stuck-at-faults:  Stuck-at-1  Stuck-at-0 Detection of a fault requires the fault to be activated and its effect observed at a primary output (PO). Fault a s-a-1 is detectable, if following conditions are simultaneously satisfied: a = 0fault is activated O a = 1“observability” is true

11. 3/30/05Agrawal: Implication Graphs11 Observability Variables Observability variable of a signal represents whether or not that signal is observable at a PO. It can be true or false. O c O a + bO a + O c bO a = 0 O C b O a = 0 a b c ObOb OaOa O c = 1 (PO) b OaOa OcOc Agrawal, Bushnell and Lin, “Redundancy Identification using Transitive Closure,” Proc. Asian Test Symp., 1996, pp. 5-9.

12. 3/30/05Agrawal: Implication Graphs12 Redundant Faults A fault that has no test is called an untestable fault. Any untestable fault in a combinational circuit is a redundant fault because it does not cause any change in the input/output logic function of the circuit. Identification of redundant faults is useful because they can be removed from testing consideration, or from hardware Fault a stuck-at-1 is redundant if either a ≡ 1no controllability or O a ≡ 0no observability or a = 0 → O a = 0no drivability or O a → ano drivability

13. 3/30/05Agrawal: Implication Graphs13 Limitation of Implication Graph a b c d e s-a-0 Implication graph (some nodes and edges not shown) Circuit with two redundant faults a bc d OcOc OdOd Implication graph shows no implications of c and d on their observabilities.

14. 3/30/05Agrawal: Implication Graphs14 Adding Partial Implications a b c c = ab Boolean false function: ab c = 0 ac + bc + abc = 0 a b c c b a Λ V Henftling and Wittmann, AEÜ, 1995 (Λ node) Λ and V nodes represent partial implications Dave, Master’s Thesis, 2004 (V node)

15. 3/30/05Agrawal: Implication Graphs15 Using Partial Implications a b c d e s-a-0 Implication graph (some nodes and edges not shown) Circuit with two redundant faults Implication Partial implication a bc d OcOc OdOd Transitive closure edge

16. 3/30/05Agrawal: Implication Graphs16 Another Example V1V1 a b c c b a Λ1Λ1 Λ2Λ2 d d V2V2 a b c d e e e Λ4Λ4 Λ3Λ3 s-a-0 s-a-1 s-a-0 s-a-1 Contrapositive of đ → ē e ≡ 0

17. 3/30/05Agrawal: Implication Graphs17 Results on ISCAS Circuits Circuit Total faults Redundant faults identified and run time TRAN Chakradhar et al. FIRE Iyer and Abramovici Imp. graph Mehta et al. Enhanced Imp. Graph Dave et al. Red. faults CPU s a Red. Faults CPU s b Red. Faults CPU s a Red. Faults CPU s a c19081879713.061.823.255.7 c2670274711595.2291.5594.0696.0 c75527550131308.0304.75111.56517.7 s1238c13556917.461.9202.6515.4 a Sun SPARC5 CPU Sec. b Sun SPARC2 CPU Sec.

18. 3/30/05Agrawal: Implication Graphs18 Referenced Methods TRAN – ATPG S. T. Chakradhar, V. D. Agrawal and S. G. Rothweiler, “A Transitive Closure Algorithm for Test Generation,” IEEE Trans. CAD, vol. 12, no. 7, pp. 1015-1028, July 1993. FIRE – Implication analysis M. A. Iyer and M. Abramovici, “FIRE: A Fault-Independent Combinational Redundancy Identification Algorithm,” IEEE Trans. VLSI Systems, vol. 4, no. 2, pp. 295-301, June 1996. Implication Graph V. J. Mehta, “Redundancy Identification in Logic Circuits using Extended Implication Graph and Stem Unobservability Theorems,” Master’s Thesis, Rutgers University, Dept. of ECE, New Brunswick, NJ, May 2003. K. K. Dave, “Using Contrapositive Rule to Enhance the Implication Graphs of Logic Circuits,” Master’s Thesis, Rutgers University, Dept. of ECE, New Brunswick, NJ, May 2004.

19. 3/30/05Agrawal: Implication Graphs19 C1908: Unidentified Redundancies 979 887 74 952 953 949 926 Redundant faults (s-a-1) 0 0 0/1 Total redundant faults = 7; identified = 5

20. 3/30/05Agrawal: Implication Graphs20 C5315: Unidentified Redundancy 1 0/1 1 1 1 1 1 PI PO 0 0 0 0 0/1 0 1 1 1 Redundant fault (s-a-1) Total redundant faults = 59; identified = 58

21. 3/30/05Agrawal: Implication Graphs21 C5315: Continued... 1 0/1 1 0 0 0 1 PI PO 1 1 1 0/1 0 1 0 Redundant fault (s-a-1) 1 1

22. 3/30/05Agrawal: Implication Graphs22 Conclusion Partial implications improve fault-independent redundancy identification – present results are the best known. Transitive closure computation run times are empirically linear in the number of nodes for benchmark circuits -- the known worst-case complexity is O(N 3 ) for N nodes. Update algorithm can efficiently compute transitive closure when implication graph has sparse connectivity. Weakness of implication method: Observability of fanout stems. Recent work has shown that some unobservable fanout stems can be identified from transitive closure analysis. Reconvergent gate Dominator a b c d Observability of a has no direct relation to observabilities of b and c, but can be related to that of d

23. 3/30/05Agrawal: Implication Graphs23 Our Students Srimat Chakradhar, NEC Qing Lin, Sun Microsystems Philip Stanley-Marbell, CMU Graduate Program Vivek Gaur, Synopsys Vishal Mehta, UCSB PhD Program Kunal Dave, ATI