1. ECE 124a/256c VLSI RC(L) Interconnect Models Forrest Brewer Wayne Burleson, Atul Maheshwari

2. Readings H. B. Bakoglu, “ Circuits interconnects and packaging for VLSI ”, Addison Wesley W. J. Dally and J. W. Poulton, “ Digital Systems Engineering ”, Cambridge Press J. M. Rabaey, “ Digital Integrated circuits : A design perspective ”, Prentice Hall

3. Components of VLSI system Logic Functional Block Logic Gates Transistors Interconnects Power/ground and Clock Inter-block Signals Intra-block Signals L2 Cache L2 Cache Processor Core Cache Tags Router Logic

4. Delay with technology scaling This figure is from the ITRS Roadmap on interconnects

5. NTRS Roadmap Year Parameter 200320042005200820112014 Technology(nm)120110100705035 # of Transistors95.2M145M190M539M1523M4308M Clock Frequency1724 MHz1857 MHz2000 MHz2500 MHz3000 MHz3600 MHz Chip Area (mm 2 )372 408468536615 Wiring Levels888-999-1010 Pitch(L/I/G)(nm)330/420/690295/375/620265/340/560185/240/390130/165/27595/115/190 A/R (L/I/G)1.6/2.2/2.81.6/2.3/2.81.7/2.4/2.81.9/2.5/2.92.1/2.7/3.02.3/2.9/3.1 Dielectric Const.2.2-2.7 1.6-2.21.5<1.5 This data is from the ITRS Roadmap on interconnects

6. Interconnect dimension trends in terms of IC generations These figures are derived from Design of High-Performance Microprocessor Circuits, A. Chandrakasan, W. Bowhill, F. Fox, IEEE, 2001

7. Rent’s rule Rent’s rule relates the I/O requirement to the number of gates as : As technology scales number of gates in a given area is increasing. More routing is required as technology scales.

8. Nature of the interconnect These figures are derived from Digital integrated circuit – a design perspective, J. Rabaey Prentice Hall and a tutorial in SLIP by Dirk Stroobandt respectively

9. Microprocessor Interconnect Global Interconnect S Local = S Technology S Global = S Die Source: Intel

10. VLSI Design Cycle Chip Specs Partitioning Floorplan RTL Timing Analysis Synthesis Timing met Layout Extraction Timing Analysis Timing met Chip Tape out

11. Early models Wire width  feature size Older technology had wide wires More cross-section area implies less resistance and more capacitance. Model wire only with capacitance L H W 

12. However… With scaling, width of wire reduced. Resistance of the wire no longer negligible. Wire not very long and a lumped RC is good enough approximation. L H W 

13. Interconnect Resistance Ohm’s Law: Resistance of wire  wire length (L) and 1/  cross-section(HW)  (resistivity) is the property of the material. L H W

14. Sheet Resistance Wire height (H) is constant for a technology. Sheet resistance ( R q ) is constant for each metal layer. Calculation of wire resistance is easy : multiply R q by L/W

15. Interconnect Capacitance Capacitance of a wire = f (Shape, Distance to surrounding wires, Distance to the substrate ) Estimating Capacitance is a matter of determining where the field lines go. To get an accurate estimate electric field solvers (2D or 3D) are used. E.g. Fastcap or Rafael When in doubt, typical wires have self capacitance between 1 and 3 pf/cm

16. Area Capacitance Dielectric Substrate Current W L H t di Electric Fields

17. Fringing Capacitance Conductor Fringing Fields  H w + w  W-H/2

18. Detailed Picture Is this much of detail required… How to compute this?

19. Interwire Capacitance

20. Wiring Capacitances (0.18  m) CapacitanceN+P+polym1m2m3m4m5m6 substrate998+2441152+201103+2139+3819+6113+559+438+253 N+ active865554211411109 P+ active8324 poly64+6918+3910+297+246+215+19 m144+6116+3510+317+235+21 m238+5415+379+277+24 m340+5615+349+31 m437+5814+40 m536+61 Units: First number is area component (af/  m 2 ), second is fringing component (af/  m)

21. How to use fringe capacitance tables Estimation of wire Capacitance Where do field lines terminate? What fraction go where? E.g. 1cm of M1 over substrate:39af/  m 2, 38af/  m fringe If 200nm wide = 0.2um, 0.2um*10,000um=2,000*39af=78fF 1cm = 10,000um, fringe on both sides: 2*38af*10,000 = 760fF Total = 848fF/cm Over Poly 64aF, 69aF – nearly doubles (half the distance to conductor)

22. Importance of Resistance Delay of wire  to the resistance of the wire. Resistance means ohmic (IR) drop along the wire, reduces noise margin. IR drop a significant problem in the power lines where current density if high. Keep wires short, to reduce resistance. Contact resistance makes them vulnerable to electromigration.

23. Metal Resistivity

24. Importance of capacitance Delay of the wire is proportional to the capacitance charged. More capacitance means more dynamic power. Capacitance an increasing source of noise (coupling). Coupling make delay estimation hard.

25. Distributed model Wire can be modeled as a distributed RC line. As the number of elements increase distributed model becomes more accurate. For practical purposes wire-models with 5-10 elements are used to model the wire.

26. Elmore Delay… First order time constant at node is a sum of RC components. All the upstream resistances are taken into account. Thus each node contributes to the delay. Amount of contribution is the product of the cap at the node and the amount of resistance from source to the node.

27. Delay in distributed RC line Elmore analyzed the distributed model and came up with the figures for delay. V in V out R1R1 C1C1 R2R2 C2C2 12 R i-1 C i-1 i-1 RiRi CiCi i R N-1 C N-1 N-1 RNRN CNCN N Elmore derived this equation in 1948 way before VLSI !!!

28. Wire Model Assume: Wire modeled by N equal-length segments For large values of N:

29. Generalized Elmore delay Rubinstein, Penfield and Horowitz generalized Elmore delay This figure is derived from Digital integrated circuit – a design perspective, J. Rabaey Prentice Hall

30. Step-response of RC wire as a function of time and space

31. RC and flight-time for a wide bus above a plane and beneath orthogonally routed layer These figures are derived from Design of High-Performance Microprocessor Circuits, A. Chandrakasan, W. Bowhill, F. Fox, IEEE, 2001

32. Pi Model Pi Model of wire: Elmore Delay = RC/3+RC/6 = RC/2 agrees with distributed model RC Pi Model is often used in Spice instead of large number of segments as a reasonable approximation of distributed RC R/3 C/2

33. Driving an RC-line Delay for FET driven distributed RC – R s is equivalent source resistance (usually assumed R s = V dd /(2 I sat )) RC gives delay for exp(-1) change in output Scale time by ln(2) = 0.69 to get typical 50% CMOS gate threshold

34. Repeaters Repeaters are buffers or inverters inserted at regular intervals. Delay linearly proportional to the wire length Questions to be answered – Where and how big should the repeaters be ?

35. Repeater placement Delay of the interconnect is typically optimum when Delay wire = Delay buffer Closed form solutions for Repeater Number and Sizing Bakoglu and Meindl, 1985 (Classical) Adler and Friedman, 1998 (considering inductance) Nalamalpu and Burleson, 2000 (ramped waveforms) Chen Marek-Sadowska, Brewer, 2003 (short channel timing) Cong, 2004 (tapered wires)

36. Bakoglu and Meindl Model For a wire with k repeaters each of size h times minimum size inverter is given by: RoRo R int, C int CoCo

37. Bakoglu and Meindl… By setting dT/dk = 0 and dT/dh = 0, optimal values for k and h are obtained Substituting these back, delay is given by

38. Optimization: Lagrange Multipliers A general technique for multi-dimensional optimization Problem: A function f(x 1, x 2, …, x n ) to maximize subject to several constraints: g 1 (x 1, x 2, …, x n ) = 0, g 2 (x 1, x 2, …, x n )=0, …, g m (x 1, x 2, …,x n ) = 0 where m<n. Solution: The n-dimensional equation above plus the m constraints provide n+m equations in n+m variables (x i ’s and j ’s) Note: it is often useful to examine the functional forms of the lambdas – they are usually interesting.

39. Best Placement for repeaters C lat -C lat Staggering the inverters Avoiding the Miller cap by opposite going signals

40. Repeater Design Issues Delay-optimal repeaters are area and power hungry – use of sub-optimal insertion Optimal placement requires accurate modeling of interconnect. Optimal placement not always possible. Performance limited due to significant interconnect resistance. Source of noise – Supply and Substrate

41. With Scaling … 1 million repeaters in a 100nm technology. Consuming about 30W (40%) in 100nm technology. Need to look at alternatives!!! 606x10 6 0 10 20 30 40 50 0.250.20.150.10.05 Technology Generation(  m) Power(W) 1x10 6 2x10 6 3x10 6 4x10 6 5x10 6 # of Repeaters Repeaters + Wire Wires Only # Repeaters

42. Differential Transmission Limiting swing saves significant amount of power. Rejects common-mode noise. Coupling is reduced due to dipole cancellation O(n 3 ) Doubled wire density -- 300mv