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**All-digital RF signal generation using ΔΣ modulation for mobile communication terminals**

Antoine Frappé Directeur de Thèse : Andreas Kaiser Equipe Microélectronique Silicium

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**Outline Background Digital transmitter architecture**

ΔΣ modulator system design Digital transmitter circuit design Experimental results Conclusion and future directions

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**Outline Background Digital transmitter architecture**

Worldwide Communications Systems Ideal Software Radio State-of-the-art in digital transmitters Digital transmitter architecture ΔΣ modulator system design Digital transmitter circuit design Experimental results Conclusion and future directions

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**Worldwide Communications Systems**

Standards diversity Europe : GSM900 / DCS1800 / UMTS Fre-quency Power Standard frequency band channel Each area has its own mobile standards Broadband standards Wi-Fi, IEEE802.11 Cordless systems DECT Short-range systems Bluetooth United-States : IS-95 / CDMA2000 China : TD-SCDMA Gabon : GSM900

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**Worldwide Communications Systems**

Bi-standard or tri-standard mobile phones GSM VOICE SMS DATA VIDEO … UMTS Single chip IS-95 Large area needed and high power consumption No reconfigurability High manufacturing cost Design of a reconfigurable RF transmitter IC able to address every standard

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**Evolution towards ideal software radio**

DAC DSP

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**Early proposed concept**

P. Asbeck et al., 2001 Concept of a digital transmitter based on bandpass ΔΣ modulation and switching PA P. M. Asbeck, L. E. Larson, and I. G. Galton, "Synergistic design of DSP and power amplifiers for wireless communications," IEEE Trans. on Microwave Theory and Techniques, vol. 49, pp , 2001.

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**State-of-the-art in digital transmitters**

J. Sommarek et al, 2004 Digital IF implementation (175MHz) ΔΣ bandwidth is 5MHz (channel width) J. Sommarek, et al., "A digital modulator with bandpass delta-sigma modulator," IEEE ESSCIRC, pp , 2004.

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**Outline Background Digital transmitter architecture**

Digital transmitter concept Proposed architecture for UMTS Architecture choices ΔΣ modulator system design Digital transmitter circuit design Experimental results Conclusion and future directions

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**Digital Transmitter Concept**

1 Digital Transmitter Concept VDD = 1V Power-DAC Digital Signal Processing 1 bit Switching-mode Power Amplifier Voltage mode Good efficiency Implemented with an inverter Generation of a 1-bit digital RF signal 1

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**UMTS standard specifications**

WCDMA access mode with Frequency Division Duplex Emission : 5MHz wide channels at 1.92 – 1.98GHz EVM < 17.5% Typical transmitter ~ 7-8% Must be increased by ~10dB for margin

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**Proposed architecture**

Fs=3.84MHz LxFs=122.88MHz 2Fc=3.9GHz 4Fc=7.8GHz UMTS: Fc=1.95GHz 30MHz 5MHz 30MHz Outside-band Noise-shaping 60MHz

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**Architecture choices (1)**

Direct upconversion Standard band frequency power Fixed carrier frequency ΔΣ-shaped quantization noise ΔΣ bandwidth Analog filter frequency response Standard band Two-step upconversion ΔΣ bandwidth power ΔΣ-shaped quantization noise Analog filter frequency response frequency Variable carrier frequency

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**Architecture choices (2)**

EXAMPLE UMTS standard IF upconversion 5MHz channel placed in [-30MHz ; 30MHz] RF upconversion [-30MHz ; 30MHz ] band placed around 1.95GHz Digital RF mixer Sampling frequency is equal to 4 x fc Interleaving operation between I and Q channels One sample on two is unused on each channel n = 0,4,8,12,…

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**Architecture choices (3)**

Q BP ΔΣ n 1 {1,0,-1,0} {0,1,0,-1} Bandpass ΔΣ implementation I Q LP ΔΣ n 1 {1,0,-1,0} {0,1,0,-1} ΔT I Q LP ΔΣ n 1 {1,0,-1,0} {0,1,0,-1} Lowpass ΔΣ implementation Equivalent complexity Digital mixer on 1 bit LP ΔΣ sampling frequency is twice lower ΔT = 1/4fc

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**Architectures choices (4)**

Q LP ΔΣ n 1 {1,0,-1,0} {0,1,0,-1} INT ΔT’ Synchronized operation Phase shift issue Resolved by interpolation on Q channel Digital upconverter output spectrum I Q LP ΔΣ n 1 {1,0,-1,0} {0,1,0,-1} ΔT ΔT’ = 1/2fc

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**Digital RF transmitter architecture**

Conclusion Based on ΔΣ modulation and switching-mode power amplification ΔΣ modulator architecture for UMTS test case Bandwidth 100MHz Sampling frequency 3.9GS/s Around 70dB of SNDR 12 effective bits ~25dB of digital gain control

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**Outline Background Digital transmitter architecture**

ΔΣ modulator system design Architecture optimization Implementation strategies Digital transmitter circuit design Experimental results Conclusion and future directions

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**ΔΣ modulator system design**

16 bits 1 bit 3rd order lowpass ΔΣ modulator Major feedback creates a 40MHz notch OSR=~40 Bandpass is ~100MHz Sampling rate is 3.9GS/s

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**Simulation results SNDR vs Amplitude level Matlab simulation results**

1 Simulation results Matlab simulation results SNDR vs Amplitude level SNDR (Signal to noise and distortion ratio) 76.6dB ENOB (Effective number of bits) ~13bits SFDR (Spurious-free dynamic range) 87.2dB 76.3dB 78.4dB -3dBFS 1

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**Architecture optimization**

Power-of-two coefficients Accumulator Integrator (minimize longest path) Signals quantization (VHDL simulations)

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Simulation results = 74.7dB = 72.2dB

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**Implementation issues**

1 Implementation issues Sample rate is 3.9GS/s (~250ps period) Critical path 4 signals to add 2 consecutive adders in the signal path Classical implementation in 2’s complement Carry propagation Incompatible with the available period 1

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**Implementation strategies**

1 Implementation strategies Borrow-Save arithmetic MSB LSB EXAMPLE Addition of 2 BS Advantages: No carry propagation Several additions at the same time Disadvantages: Twice more bits to implement Full custom design 1

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**Implementation strategies**

Borrow-Save arithmetic Sample rate 3.9GS/s 250ps period FA FA FA FA FA Borrow-Save arithmetic instead of 2’s-complement No carry propagation and constant-time additions Maximum delay in critical path is 3.δ(FA) Design of a logic cell with a delay less than 250ps / 3 ~ 80ps - Differential dynamic logic cells controlled by 3-phase clocks (DLL) Logic comparator

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**Implementation strategies**

Non-exact quantization New problem: Sign evaluation needs carry propagation 5MHz 10MHz 2’s complement 74.7dB 72.2dB Ideal BS 76.2dB 73.7dB Truncated BS 68.8dB 67.4dB Performances remain good with low complexity

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**Implementation strategies**

Output Signal Precomputation Sample rate 3.9GS/s 250ps period FA FA FA FA FA FA

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**ΔΣ modulator system design**

Conclusion Implementation of a very high-speed digital ΔΣ modulator with : redundant arithmetic non-exact quantization output signal precomputation Covered by a patent FR (US application in progress)

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**Outline Background Digital transmitter architecture**

ΔΣ modulator system design Digital transmitter circuit design IC block structure and chip overview ΔΣ core layout Experimental results Conclusion and future directions

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IC block structure

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**First chip overview in 90nm CMOS**

1 First chip overview in 90nm CMOS Compensation cell Q inputs VddDS VddCLK VddANA Clock shaper & DLL ΔΣ core & Sample rate conversion Clock tree (adjusted to equalize the delay) Output buffers I inputs Multiplexer 3mm (Without M7) 1mm 1

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**ΔΣ core layout Area : ~8000 transistors 350 x 160µm² = 0.056mm² Slice**

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1 Slice example layout Full Adder 1

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**Sum (or carry) calculation block :**

1 Dynamic logic style Sum (or carry) calculation block : Sum evaluation Sum dynamic logic Carry evaluation Carry dynamic logic Can be modified to obtain any logic function 1

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**Outline Background Digital transmitter architecture**

ΔΣ modulator system design Digital transmitter circuit design Experimental results First and second chip overview Test setup Headlines of measurement results Comparison with other works Conclusion and future directions

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**First chip test & Measurement results**

Measurement results on output stages 2 main issues for core functionality: Oscillations on power and ground inside the chip Bad initialization of the delta-sigma core Corrections are implemented on a second chip in 90nm CMOS

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**Second chip overview (90nm CMOS)**

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**Test setup .m DUT 10MHz reference Matlab File with WCDMA signal**

7.8GHz frequency synthesizer .m Master clock Bias tee IQ MS/s + data clocks IQ MS/s + data clocks DUT DC block FPGA CycloneII with upconverting & filtering software Arbitrary Waveform Generator (AWG420) or Pattern Generator Balun Spectrum analyzer or Digitizing oscilloscope

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**Headlines of measurement results**

Full functionality up to 4GHz (instead of the expected 8GHz rate) Standard bands addressed up to 1GHz Maximum bandwidth is 50MHz (proportional to the sampling rate) RF output spectrum RF output spectrum

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**SNDR measurement SIMULATION of the ΔΣ core ~20dB MEASUREMENT**

Input : sine wave

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**Digital core functionality**

Eye diagram at the RF output Jitter = 13.24psRMS MUX 4fc Example of an output spectrum with a DC input and a 2.5GHz clock (single-ended output) Analog output Digital data stream

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**Measurement results (2.6GHz clock) (1)**

UMTS test case (fc=1.95GHz) Measurements at a 2.6GHz clock frequency Fundamental band at 650MHz Image band at 1.95GHz (degraded results) Relative bandwidth is 30MHz 10.45dB power sinx/x Relative bandwidth f s/4 3fs/4 fs frequency

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**Measurement results (2.6GHz clock) (2)**

5MHz QPSK channel with -3dBFS power 650MHz fundamental band ACPR~52dB 5MHz -10MHz -5MHz +5MHz +10MHz 1.95GHz image band ACPR~44dB -10MHz -5MHz 5MHz +5MHz +10MHz

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**Measurement results (2.6GHz clock) (3)**

ACPR ACPR vs amplitude for fundamental and image bands 5MHz QPSK channel with 8.1dB PAPR VHDL SIMULATIONS : ACPR max = 74.7dB

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**Measurement results (2.6GHz clock) (3)**

EVM UMTS EVM requirements : <17.5% Typical transmitter EVM : 7~8% 5MHz QPSK channel with -3dBFS power 650MHz band 1.95GHz band

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Power consumption

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**Summary of measurements**

2.6GHz clock 650MHz channel 1.95GHz channel (image) ACPR (5MHz wide channel) 53.6dB 44.3dB Max Channel Power -3.9dBm -15.8dBm EVM 1.24% 3.42% Output jitter 13.2psRMS SNDR (BW = 30MHz) 40.3dB In-band noise floor -129.5dBm/Hz -129.4dBm/Hz Peak output power 3.1dBm -8.59dBm Power consumption total 69mW (1V) output stages 39mW core 2 × 15mW

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**Comparison with other works**

This work [1] Max Clock Frequency 4GHz clock 700MHz clock Max Carrier Frequency 1GHz channel 3GHz channel (image) 175MHz channel Max Adjacent ACPR (5MHz wide channel) 500MHz clock 2.4GHz clock 50.26dB Max Alternate ACPR (5MHz wide channel) 500MHz clock 2.4GHz clock 40.27dB Total Power Consumption 25mW 700MHz clock 69mW 2.6GHz clock 139mW 700MHz clock Total Silicon Area 3.2mm² (core: 0.06mm²) 5.2mm² (core?) Process 90nm CMOS (GP) 130nm CMOS [1] J. Sommarek, et al., "A digital modulator with bandpass delta-sigma modulator," IEEE ESSCIRC, pp , 2004.

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**Comparison with other works**

1 Comparison with other works [2] Digital-to-RF converter (DRFC) 2nd order MASH ΔΣ modulator providing 3-bit input signals SNR=30dB over 200MHz Current-mode output stage ΔΣ sampling frequency is 2.5GS/s simple structure 1 10bits 2 3bits DS à 2.5GS/s mais stucture très simple [2] A. Jerng and C. G. Sodini, "A Wideband Delta-Sigma Digital-RF Modulator for High Data Rate Transmitters," IEEE J. Solid-State Circuits, vol. 42, pp , 2007. 1

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**Comparison with other works**

1 Comparison with other works [3] DRFC with 10-bit 307.2MS/s oversampled input signals 41/56dB ACPR (for 5MHz channels and 25dBm output power) EVM<2% over 60dB of control range 1 10bits 2 3bits DS à 2.5GS/s mais stucture très simple [3] P. Eloranta, et al., "A WCDMA Transmitter in 0.13µm CMOS Using Direct-Digital RF Modulator," ISSCC Dig. Tech. Papers, pp , 2007. 1

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**Outline Background Digital transmitter architecture**

ΔΣ modulator system design Digital transmitter circuit design Experimental results Conclusion and future directions Conclusion and discussion Future work

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Conclusion First reported transmitter chain using 1-bit digital RF delta-sigma modulation Borrow-Save arithmetic Non-exact quantization Prototype demonstration in 90nm CMOS Measurement results for a clock frequency until 4GHz Good performances of the digital ΔΣ modulator Analog RF output performances to be improved For UMTS Possibility to use the first image band with a 2.6GHz clock with slightly degraded results

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**Future directions (1) Integration inside a whole transmitter chain**

European IST MOBILIS project Higher frequency functionality? Analysis of the critical issues (clock input, logic, parasitics…) Solutions for higher frequency operation Implementation of a prototype in a faster technology (65nm CMOS or 65nm SOI CMOS)

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**Future directions (2) Reduction of out-of-band noise**

Higher order ΔΣ modulators Complex ΔΣ modulator architectures Digital RF filtering Study of reconfigurability issues Discussion on output stage Voltage-mode vs. current-mode Single-bit vs. multi-bit

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**Publications & Conferences**

International Conferences A. Frappé, B. Stefanelli, A. Flament, A. Kaiser, A. Cathelin, “An all-digital delta-sigma RF signal generator for mobile communication transmitters in 90nm CMOS”, to be submitted to RFIC 2008. A. Frappé, A. Flament, B. Stefanelli, A.Kaiser, A. Cathelin, R. Daouphars, “Design techniques for very high-speed digital delta-sigma modulators aimed at all-digital RF transmitters”, IEEE International Conference on Electronics, Circuits and Systems, ICECS 2006, Nice. A. Frappé, A. Flament, B. Stefanelli, A. Cathelin, A. Kaiser, “All-digital RF signal generation for software defined radios”, IEEE International Conference on Circuits and Systems for Communications, ICCSC 2006, Bucarest, pp C. Nsiala Nzéza, A. Frappé, J. Gorisse, A. Flament, B. Stefanelli, A. Cathelin, A. Kaiser, “Direct digital RF signal generation for Software-Defined Radio transmitters using reconfigurable Delta-Sigma modulators”, Proceedings of the 11th International Symposium on Microwave and Optical Technology (ISMOT-2007), Monte Porzio Catone, Italy, December 2007, to appear. C. Nsiala Nzéza, J. Gorisse, A. Frappé, A. Flament, A. Kaiser, A. Cathelin, « Reconfigurable digital delta-sigma modulator synthesis for digital wireless transmitters », Proceedings of the IEEE European Conference on Circuit Theory and Design, ECCTD 2007, Sevilla, Spain, August 2007, pp National Conferences and Symposiums A. Frappé, A. Flament, B. Stefanelli, A. Cathelin, A. Kaiser, “All-digital RF signal generation for software defined radio transmitters”, Colloque du GDR SoC-SiP 2007, Paris. C. Nsiala Nzéza, A. Frappé, J. Gorisse, A. Flament, B. Stefanelli, A. Kaiser, “Reconfigurable RF signal generation for software radio transmitters”, Actes du 8ème colloque sur le Traitement Analogique de l’Information, du Signal et ses Applications (TAISA’2007), Lyon, France, Octobre 2007, pp A. Flament, A. Frappé, B. Stefanelli, A. Kaiser, A. Cathelin, « Convertisseur numérique analogique 1 bit à 7,8Gech/s pour émetteurs RF numériques en technologie CMOS 90nm », in TAISA 2006, Strasbourg, pp Patents A. Frappé, A. Kaiser, A. Cathelin, « Procédé de traitement d’un signal numérique au sein d’un modulateur delta-sigma, et modulateur delta-sigma numérique correspondant », FR filled on January 16th US application filing request.

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