1. Status of measurements of FE-I4 Efuse SEU and PRD P.Breugnon, M.Menouni, R.Fei, F.Gensolen, L.Perrot, A.Rozanov, 22.06.2011

2. Efuse errors, IoMux and GR errors at start of run Maurice and Abder proposed to use IoMux setting to configure correctly Efuse memory refresh (bug in the design) by setting IoMuxSelP(0,pin73)=1, IoMuxSelP(1,pin72)=1, IoMuxInP(0,pin74)=1, all other IoMux to zero. Thanks to Joern who immediately implemented IoMux bits settings into STControl software in IOBoard menu. Chip#28 does not work with IoMux bits ON. Reason was understood: dead driver of IoMuxSel0 signal on interface board#36. Original defect or irradiation ??? Chip#27 works with nominal Vdda=1.5 V. Also works at Vdda=1.4 volts only after 24 hours cooling down, but not during the beam or short stops. In all other combinations does not work, see Richun’s table.

3. IoMux condition matrix from Richun

4. Classification of the errors in Efuse “Reload from PROM” - EfuseCref 15->0 “Coherent Efuse” several wrong Efuse words together “Normal SEU” one bit wrong in Efuse “Scotching “ scotching many bits in many words both to zero and 1.

5. Results on GR tests run 89 chip27 IoMux bits set to 1, Vdda=1.5 V “Reload from PROM” High rate 0.16 err/spill (12/73) of EfuseCref 15->0 Expected rate from GR = 0.068 (64bits/>240bits)<0.017 but SR31=0. Too short pulses by Mohsine ? SR21~55-80,sr24=0, sr25=0-2 “Coherent Efuse” High rate 0.06 err/spill (4/73) (4-6 words together) SR21~60-70, SR24=0, SR25=0-2,SR31=0 Too low(??) rate of PRD 0.015 err/spill (1/73) One event of “Normal SEU” (ChipLatency 210->146) Run ended by scotching many bits in ~10 words both to zero and 1 in iterations 183-393.

6. Results on GR tests run 90 chip27 IoMux bits set to 1, Vdda=1.5 V “Reload from PROM” High rate 0.15 err/spill (9/62) EfuseCref 15->0 SR21~42-67 sr24=0, sr25=0-2 sr31=0 “Coherent Efuse” High rate 0.08 err/spill (5/62) (2-7 words together) SR21~60-70, SR24=0, SR25=0-2, SR31=0 Too low(??) rate of PRD 0.016 err/spill (1/62) no events of normal SEU Run ended by hang up

7. Control results on GR tests run 89 chip28 IoMux bits set to 0, Vdda=1.5 V PRD rate 0.06 err/spill (18/284) SR21~127-203 sr24=0, sr25=0-2 sr31=0 WriteRegError glitch rate 0.007 err/spill (2/284) SR21~130-165, SR24=0-2, SR25=4-790, SR31=0 Internal GM glitch rate 0.011 err/spill (3/284) no events of normal SEU This run was in parallel with runs 89-90 chip27. As the rates are compatible with preveous runs, it proves that low PRD rate in chip27 with IoMux bits is not due to unusual beam conditions

8. Annealing of the chip27 In the beam and short stops chip 27 was working at GR test with IoMux bits set to 1, Vdda=1.5 V, but does not work with Vdda=1.4 V and lower After 24 hours of annealing at room temperature this chip was working at Vdda=1.4 V, but not at Vdda=1.3V After 48 hour of aneealing Chip 27 was working at GR tests with Vdda=1.4, 1.3, 1.2,1.1,1.0 V

9. Conclusions Basics functionality of Efuse are demonstrated for chip#27 High Efuse reload rates 16% while <1.7% expected: Why ? Is Efuse_error pulse on SR31 too short to be seen in counters ? High Efuse coherent rate 6-8 % Why ? Glitch on Write responsible ? Again abnormal run end with some scotched Efuse bits. Lower SR21 single PRD rate ~60 with IoMux=1 instead of 130-200 in case IoMux=0 Lower PRD reset rate 1.5% with IoMux=1 instead of 6.0%? Why chip 27 show annealing effects with Vdda=1.4 and IoMux =1?

10. Spare