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1 Patrick Breugnon, Richun Fei, Denis Fougeron, Maurice Garcia-Sciveres (*), Fabrice Gensolen, Mohsine Menouni, Laurent Perrot, Alexandre Rozanov CPPM.

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Presentation on theme: "1 Patrick Breugnon, Richun Fei, Denis Fougeron, Maurice Garcia-Sciveres (*), Fabrice Gensolen, Mohsine Menouni, Laurent Perrot, Alexandre Rozanov CPPM."— Presentation transcript:

1 1 Patrick Breugnon, Richun Fei, Denis Fougeron, Maurice Garcia-Sciveres (*), Fabrice Gensolen, Mohsine Menouni, Laurent Perrot, Alexandre Rozanov CPPM - CNRS - Université de la Méditerranée - Marseille Vienna TWEPP 2011 September 27 th 2011Vienna TWEPP 2011 – SEU WG (*): Lawrence Berkeley National Laboratory

2 2 Latches pixel implementation Description implementation Memory for global configuration Experimental test setup Beam profile Results Latch pixel Cross section Analog scan Global memory Cross section Improvement Conclusion September 27 th 2011Vienna TWEPP 2011 – SEU WG

3 3 FEI4_A chip (~ 4cm²) DICE latch (Version A : 32 µm²) DICE latch (Version B: 41 µm²) September 27 th 2011Vienna TWEPP 2011 – SEU WG FEI4_A: 336 rows x 80 columns = pixels x 13 latches per pixel = configuration latches of pixels There are 2 kinds of latches inside this chip: Version A : DICE latch structure with linear NMOS and PMOS implemented in 30 double columns Version B : DICE latch issue to SEU chip using enclosed NMOS, PMOS linear and guard ring are implemented in 8 double columns We extract this last version latches from previous SEU measurements we did at CERN with a dedicated chip

4 4 The DICE latch consists of 2 elementary memory cells to form the 13 bits configuration memory of the pixel. In order to separate sensitive pair nodes and improve the SEU tolerance, we used interleaved layout for each latch in the pixel configuration bloc (as shown next) Delicate operation for several reasons: It increases the dedicate area (+25%) It complicates the interconnection between elementary cells Interleaved structure version B 1 elementary cell=2 inverters 166µm 50µm 37µm 30µm 22µm DICE latch A1A2 Layout of one pixel A1 C2 B1 D2 C1 A2 D1 B2 E1 G2 F1 H2 G1 I2 H1 E2 I1 F2 A1 C2 B1 D2 C1 A2 D1 B2 September 27 th 2011Vienna TWEPP 2011 – SEU WG

5 5 512 bits are stored in a Triple Redundant DICE Latches (TRL) TRL Cell area : 27µm × 19µm Bloc area : 900 µm × 360µm Errors are determined with comparing the Read -back data to the loaded data September 27 th 2011Vienna TWEPP 2011 – SEU WG 5:32 decoder Memory cell Layout of the global memory (900µmx360µm) DICE 1 DICE 2 DICE 3

6 6 Irradiation zone ~20 meters length USB cable ~3 meters Control room Power Supply VDDD-VDDA USBPix software MultiIO board - USB controller - FPGA -.. Adapter card - Regulators - LVDS /TTL translators Power Supply Data 2 FEI4_A chips as target of the beam USB controller initialization Power supply monitoring Sequence is described by a primlist Pixel tests DAQ control is performed by the Bonn and Göttingen university team. Thanks to Malte Backhaus and Joern Grosse-Knetter who came help us to adapt this software to SEU measurement application. September 27 th 2011Vienna TWEPP 2011 – SEU WG

7 7 Irradiation tests were carried out using IRRAD3 beam line of the Proton Synchrotron (PS) CERN irradiation facilities (East Hall). https://irradiation.web.cern.ch/irradiation/ The test beam provides a beam of 24 GeV protons Supercycle with 36x1.2=43.2 sec period (can change) It contains several spills of particles: The duration of each spill is 400 ms, Spot area around 1 cm² (as shown next) Typically 2 spills of protons, but sometimes more because we share the beam with others experiments (up to 4 spills). This last point complicates SEU calculations, it can create a risk of overlap between spill and the operation of reading or writing data. X and Y beam profile with 3 spills (CSA ouputs) September 27 th 2011Vienna TWEPP 2011 – SEU WG beam profile during an analog scan-run171 chip 27 spill1 mm

8 8 Conditions to measure this cross sections : Beam centered on the chip center for pixel latches SEU measurements We compare the pattern on 2 double columns (1 pixel per column 336 lines x 2 = 672 bits) Proton intensity up to~ protons/spill Pixel latches with optimized layout (Version B) are 30 times more resistant to SEU than the version B Absolute values of cross section are not yet final Al foil scans to be analyzed Analog scan doesn’t give exactly the same value Several beam conditions (with/without septum losses) to be analyze. Rate/spill Cross-section 0->1 1->0 Pixel latches (version A) cm -2 Pixel latches (version B) cm -2 September 27 th 2011Vienna TWEPP 2011 – SEU WG Cross section table

9 9 Conditions to obtain this map: Beam centered near to the chip center Proton intensity ~ protons/spill All pixels disabled after each spill (corresponding to one latch per pixel) Analog scan with 200 events after one or several spills An upset from 0 to 1 of the pixel enable bit will give the map corresponding to the respond of the input injection charge (200 events per input). In this configuration, we can directly see: the difference of behavior between 2 kinds of latches and lower SEU rate clearly seen in version B columns, the shape of the beam September 27 th 2011Vienna TWEPP 2011 – SEU WG Latch upset map in PS run for one spill DICE latch (version A)DICE latch variant (version B) mm

10 10 Conditions to obtain this cross sections Beam centered near to the end of columns for the Global register measurements Proton intensity up to ~ protons/spill The Error rate is 0.016/spill It is 8 times higher than the estimated value A deep analysis of errors show that the most of them are caused by glitches Rate/spill Cross-section 0->1 1->0 GR glitches cm -2 GR DICE errors cm -2 September 27 th 2011Vienna TWEPP 2011 – SEU WG Cross section table (per bit)

11 11 The load input signal is common to the 3 latches of the cell memory: A glitch in the internal NAND or inverter causes a glitch on the load signal. In this case the current value on the data bus is copied in the memory and can create an error. In order to reduce the sensitivity to glitches, we triplicate the load path This cell has been modified in the new submitted version of FEI4 chip (FEI4-B), we hope to reduce considerably this sensitivity from to errors/spill where a value that comes from previous measurements. September 27 th 2011Vienna TWEPP 2011 – SEU WG Memory cell unit schematic New load path

12 12 2 versions of DICE configuration pixel Latch were implemented and are tested now since June 2011 at CERN We can obtain directly a comparison of their behaviors with the same profile of beam The direct measurement of error rate show a gain of ~ 30 between these two versions The version of Global Memory was modified for the FEI4_B in order to improve the SEU rate and minimize glitches error. Work to do: improve the error rate calculation Absolute protons flux with Al foils refine the calculations with analog scan (more accuracy with the beam shape) study different beam shape (with/without septum losses) … September 27 th Vienna TWEPP 2011 – SEU WG


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