1. Petry1 MAPLD 2005/120 2005 MAPLD International Conference Washington, D.C. The Impact of Silicon Etch Dislocations on EEPROM Cell Reliability Presented by: David Petry Director of Quality Assurance

2. Petry2 MAPLD 2005/120 Abstract: The relationship between silicon etch dislocations and EEPROM cell reliability will be discussed in this paper. »The point of view is from ZMD’s own floating gate EEPROM design, process yield, field experience and failure analysis efforts. »Silicon dislocations occur naturally in CMOS semiconductor processes but have a greater impact on IC reliability at high operating temperatures. The use of wafer level high temperature screens will be discussed focusing on their use to reduce PPM defect levels. »A detailed review of an EEPROM cell failure will be discussed and how this evaluation utilized the 8D approach to aid problem solving and the development of subsequent corrective actions.

3. Petry3 MAPLD 2005/120 Reliability Test:

4. Petry4 MAPLD 2005/120 Failure Rate Calculation: Note: 3 lots of 77 pcs. tested

5. Petry5 MAPLD 2005/120 EEPROM Data Retention: Wafer test results: We have tested product: Approx. 570 wafers at Wafer test 2 and 150 wafers at Wafer test 3 (always 25°C test of EEPROM with checker board pattern). Between the Wafer test 1 and 2 and between Wafer test 2 and 3 is a bake step (with a temperature of 250°C and a duration of 22 h).

6. Petry6 MAPLD 2005/120 EEPROM Data Retention: In total, we tested 719,610 die and found 533 data retention failures post 22 hour bake that means 0.15% data retention failures. Calculate failure rate for use condition of 55°C average temperature, this results in: (# of failures / tested die * bake time * acceleration factor) => 533 / [359805 * 22 h * 1994480] => 0.034 FIT Incidentally, a 22-hour bake at 250C represents 5008 years of EEPROM use at +55C based on the acceleration. Acceleration factor is based on Arrhenius equation.

7. Petry7 MAPLD 2005/120 Benchmarking: There is a strong consensus in the technical literature of the semiconductor industry that a bake between 150 to 250C for a duration of 2 to 24 hours is sufficient to reduce the early failure rate of typical CMOS EEPROM data retention endurance failure modes. The ZMD selected value was determined based on the following: 1)Industry benchmarking and comparison, 2)Review of our CMOS process, and 3)Consideration of customer suggestions and experience. But…is this good enough for high reliability applications?

8. Petry8 MAPLD 2005/120 Problem reported in Automotive ASIC: Customer experienced a single failure with one EEPROM cell not being able to be read properly. Cell “floating gate” value was flipping between “0” and “1” value at room temperature. Part failed post thermal shock. Failure verified by ZMD and it was noticed that there was a temperature dependency, i.e. state of cell could be toggled by lowering the device temperature. High temperature stress was applied to understand behavior of cell.

9. Petry9 MAPLD 2005/120 8 Disciplines Process for problem solving: 1.Define the Team 2.Problem Description 3.Definition and verification of short-term containment actions 4.Definition of Root cause(s) 5.Selection of Permanent Corrective Action(s) 6.Implementation of Permanent Corrective Action(s) 7.Action(s) to prevent problem recurrence 8.Problem solved (celebrate)

10. Petry10 MAPLD 2005/120 Failure Analysis steps: Application of high temperature stress resulted in a change to the trip point temperature. So the cell was still leaking and was sensitive to thermal stress. Corner cell of the matrix. Time to “peel back the onion”…

11. Petry11 MAPLD 2005/120 Failure Analysis steps: Potential voltage contrast (PVC) image of layer 1 metal

12. Petry12 MAPLD 2005/120 Failure Analysis images: SEM picture with marked failed cell (circled in green). Note layer 1 metal is removed.

13. Petry13 MAPLD 2005/120 Failure Analysis images: SEM image of the tunnel window of the failed cell with the tunnel oxide is removed (high magnification) SEM image of a tunnel window in the neighborhood cells

14. Petry14 MAPLD 2005/120 Failure Analysis images: SEM picture of the complete failed cell after 30 s Wright etch Dislocations

15. Petry15 MAPLD 2005/120 Failure Analysis images: Dislocation Higher magnification

16. Petry16 MAPLD 2005/120 Definition of Dislocations: Dislocations are defects in crystalline materials like silicon. Where dislocations intersect a surface, a feature called an etch-pit can form after etching the silicon. The pit formation is due to the enhanced etching rate at lattice defects. Dislocations are an expected occurrence in silicon based microelectronic devices and usually are not a problem due to the purity and quality of the Si wafers used.

17. Petry17 MAPLD 2005/120 Ishikawa / Fishbone Diagram:

18. Petry18 MAPLD 2005/120 Failure Analysis images: Floating gate area Cell Write circuit Tunnel Oxide Cell Read Circuit

19. Petry19 MAPLD 2005/120 Failure Analysis images: Backpreparation of this device from customer that passed all testing. Each device shows a low density of dislocations in the key active circuit area. Note that some small amount of dislocations is normal.

20. Petry20 MAPLD 2005/120 Intel studies show… Dislocations can cause subtle source-drain leakage. One study found dislocation as root cause of MOS transistor failure. Use Wright Jenkins Etch for 10 seconds; control of staining time is critical. Easy to over etch. Failures detected by using high supply voltage Vcc and high temperature (+95C).

21. Petry21 MAPLD 2005/120 ST Microelectronics studies show…. In one study, they observed that corner regions of memory arrays are more prone to dislocation failures. Cause of dislocations is mechanical stress and the ion implantation process. Dislocation defects can be eliminated by careful process control and suitable high temperature thermal annealing temperatures in order of 900C or higher.

22. Petry22 MAPLD 2005/120 Microchip studies show…. Single cell EEPROM failures usually occur early in the parts life. Typical activation energy of 0.12ev was seen. Writing all zeros or all ones to EEPROM is more stressful than “checkerboard” pattern. Memory failure rates due to silicon defects and dislocations, imperfections in oxide, silicon-oxide interface or poor silicon manufacturing process controls. Programming temperature is a wear out accelerator. The combination of temperature & high voltage is useful for early defect detection.

23. Petry23 MAPLD 2005/120 Failure Mechanism found ! Read circuit Pit caused by electrical overstress. May have started out as a dislocation. Region damaged by electrical overstress; the area was altered by current to ground.

24. Petry24 MAPLD 2005/120 Failure Mechanism: The failure mechanism for the single bit failure was caused by electrical overstress (EOS) in the bit line circuitry at the read select transistor of the floating gate cell. There is physical evidence of this EOS damage; see prior photograph. The added resistance from the Gate to Drain on the select transistor caused the "1" to be read as a "0" since it creates a voltage divider with the Drain to Source impedance. Probable failure mode is that a silicon defect transformed into an EOS site after thermal shock test resulting in the changed circuit characteristic.

25. Petry25 MAPLD 2005/120 Corrective actions: ZMD would like to reduce the defect density of dislocations. A separate DOE effort is planned and will improve the reliability and yield of all ZMD IC products. The containment of similar single bit errors is best done using a rigorous wafer level screen. Increasing the endurance programming operating temperature (coupled with high voltage) will aid the detection of defect leakage currents if they are present. Additional writing all 0’s to the EEPROM after the checkerboard tests will assure that the EEPROM cells are capable of this stringent condition.

26. Petry26 MAPLD 2005/120 Containment: Modified test flow for EEPROM circuitry (changes in RED): 1. Endurance test with 40 cycles at 70 degrees Celsius: write "1's" in all cells and then "0's" in all cells etc. 2. Conduct an address test where all addresses are written with checkerboard pattern followed by compare. Then all addresses are written with inverse checkerboard and compared. 3. Write all cells with "0's", read back with a compare. Write all cells with "1's", read back with a compare. 4. Bake 22 hour with 250 degrees Celsius. 5. Finally, the content of all cells are compared with "1's" (verify data retention).

27. Petry27 MAPLD 2005/120 DOE results: Specific types of dislocations were created when 3 process factors were varied in the experiment… but higher thermal annealing temperature can reduce occurrence of dislocations.

28. Petry28 MAPLD 2005/120 Conclusions: Use the 8D process to organize your evaluation. Silicon defects and dislocations can have subtle effects on gate leakage current and thus impact the reliability of EEPROM memories. Develop robust wafer level screens for the detection of weak cells. Use Design of Experiments to dramatically reduce silicon defects and dislocations. Introduce process changes carefully.