1. EMC of ICs Practical Trainings

2. 2 May 15 Objectives Get familiar with IC-EMC/Winspice Illustrate parasitic emission mechanisms Understand parasitic emission reduction strategies Power Decoupling Network modelling Basis of conducted and radiated emission modelling Basis of immunity modelling

3. 3 May 15 Summary IC-EMC – Reference Basic concepts  Ex. 1. FFT of typical signals  Ex. 2. Transient current estimation  Ex. 3. Interconnect parasitics  Ex. 4. Impedance mismatch  Ex. 5. Crosstalk Emission  Ex. 6. di/dt noise  Ex. 7. PDN modeling Case study: Optimization of Starcore PCB (ICEM model)

4. 4 May 15 IC-EMC - Simulation flow IC-EMC schematic Editor (.sch) IC-EMC model libraries WinSPICE compatible netlist generation (.cir) WinSPICE simulation IC-EMC Post-processing tools (emission, impedance, S-parameters, immunity) Measurement import Output file generation

5. 5 May 15 Open schematic (.sch)Build SPICE netlist (.cir) Save schematic (.sch)Spectrum analysis Delete symbolsNear field emission simu. Copy symbolsImmunity simulation Move symbolsTime domain analysis Rotate symbolsImpedance simulation Flip symbolsS parameter simulation Add Text lineIbis file editor Add a lineParametric analysis View electrical netSymbol palette Zoom in/outView all schematic IC-EMC – Most Important Icons

6. 6 May 15 −Click on WinSPICE.exe −Click File/Open to open a circuit netlist (.cir) generated by ic-emc. −IC-EMC main commands (text line): Simulation commandCommand lineParameters Transient simulation.tran 0.1n 100n step + stop time DC simulation.DC Vdd 0 5 0.1 source + start + stop + step Small signal freq. analysis.AC DEC 100 1MEG 1G sampling + nb points + start + stop Load SPICE library.lib 65nm.lib Path and file name IC-EMC – Link to WinSpice

7. 7 May 15 7 Create the schematic Set the source generator Transient simulation FFT by IC-EMC Simulate the FFT of a sinus and a square signal Exercise 1. FFT of typical signals

8. 8 May 15 8 Exercise 1. FFT of typical signals FFT of a sinus source –Set the voltage generator properties: Frequency = 1 GHz Amplitude = 1 V 8 Ex1-FFT-sinus.sch

9. 9 May 15 FFT of a sinus source –Type the simulation command:.tran 1n 50n –Simulate the response in time domain. –Compute the FFT. –Does the FFT result correlate with theoretical result ? Exercise 1. FFT of typical signals

10. 10 May 15 FFT of a square current source –Set the generator properties –For example: Period = 10 n, PW = 4 n, Tr = 1n, Tf = 1 n V0 = 0 V, V1 = 1 V Exercise 1. FFT of typical signals Ex1-FFT-Pulse.sch

11. 11 May 15 FFT of a square source For a square signal (Tr=0) For a trapezoidal signal (Tr=Tf) Exercise 1. FFT of typical signals

12. 12 May 15 Standard cell inverter in CMOS technology Typical load capacitance Observe in time domain the current through Vss. Exercise 2. Transient current estimation Ex2-transient_inverter.sch

13. 13 May 15 Time domain simulation Adjust scales (Autofit and zoom on time axis) Exercise 2. Transient current estimation

14. 14 May 15 What is the influence of the load capacitance (1 fF to 1 pF) ? C load I peak C load Rise time Exercise 2. Transient current estimation

15. 15 May 15 –The core is mounted in a QFP64 package. –A pair of pins is dedicated to supply the core 0.7 mm 12 mm 0.22 mm 25 µm 3.5 mm 6 mm 1.5 mm Exercise 3. Interconnect parasitics Evaluate the electrical parasitic associated to the power supply pair.

16. 16 May 15 Use Tools/Interconnects Parameters to evaluate R, L, C associated to package pins. Empirical estimation : Lead : L = 0.5 nH/mm and C = 0.1 pF/mm Bonding : L = 1 nH/mm Exercise 3. Interconnect parasitics

17. 17 May 15 Exercise 4. Impedance Mismatch –Let’s consider the following link between 2 digital inverters. No matching is placed at each termination. –The digital inverters are 74AHCT04, from NXP. The IBIS file ahct04.ibs is given. –Build a SPICE model to evaluate the signal integrity at each termination of this digital link. 5 V power supply + filtering 1 st inverter: output driver 2 nd inverter: input driver 1 MHz square signal 10 cm 120 Ω microstrip line Section of the line Top layer (signal line + power) Bottom layer – GND plane FR4 (εr = 4.5) 35 µm 1.6 mm W = 0.36 mm

18. 18 May 15 Exercise 4. Impedance Mismatch –From IBIS file, propose an equivalent model for input and output driver. –“File > Load IBIS” ahct04.ibs Package outline Functional diagram Input Output

19. 19 May 15 Exercise 4. Impedance Mismatch –Proposed models for input and output driver. IBIS_input_buffer_IV.Sch Measured I(V) charac. Of output buffer Measured I(V) charac. Of input buffer IBIS_buffer_out_carac_IV.sch

20. 20 May 15 Exercise 4. Impedance Mismatch –Verify the theoretical characteristic impedance of the microstrip line (“Tools > Interconnect Parameters”). –The following S11 measurements have been done: Line open (zin-line120-open.s1p) Line loaded by 51 Ω resistor (zin- line120-load51.s1p) Line loaded by 120 Ω resistor (zin- line120-match.s1p) –Propose an equivalent model for the line. zin-line120-open.s1p zin-line120-match.s1p

21. 21 May 15 Exercise 4. Impedance Mismatch –Build the complete electrical model of the digital link. –Simulate the transient response of signal at each termination of the link. –Validate your model from measurements: Rising waveform at output driver (rw_out_no_match.tran) Falling waveform at output driver (fw_out_no_match.tran) Rising waveform at input driver (rw_in_no_match.tran) Falling waveform at input driver (fw_in_no_match.tran) Output driver Input driver

22. 22 May 15 Exercise 4. Impedance Mismatch –Two solutions are proposed to improve signal integrity: Place two 120Ω resistors at both line terminals Place one 120Ω resistor at output driver side, one 120Ω resistor and a serial 4.7 pF capacitor –Test the effect of both solutions. –Validate your models from measurements: Rising waveform at output driver (rw_out_matchR.tran and rw_out_matchRC.tran) Falling waveform at output driver (fw_out_matchR.tran and fw_out_matchRC.tran) Rising waveform at input driver (rw_in_matchR.tran and rw_in_matchRC.tran) Falling waveform at input driver (fw_in_matchR.tran and fw_in_matchRC.tran) Input driver – R matching Input driver – RC matching

23. 23 May 15 Exercise 5. Crosstalk 23 May 15 –Let’s consider the following link between 2 digital inverters (74AHCT04). No matching is placed at each termination. –A second line loaded by 47 Ω at each terminals is placed at close distance (2W) –Build a SPICE model to evaluate the crosstalk at each termination of the victim line (near-end and far-end). 5 V power supply + filtering 1 st inverter: output driver 2 nd inverter: input driver 1 MHz square signal Aggressor line Section of the line Top layer (signal line + power) Bottom layer – GND plane FR4 (εr = 4.5) 35 µm 1.6 mm W = 1 mm Victim line W = 1 mm 2W

24. 24 May 15 Exercise 5. Crosstalk –Build the complete electrical model of the coupled lines. –Simulate the transient response of signal at each termination of the victim line. –Validate your model from measurements: Near end crosstalk (NE_ctlk.tran) Far end crosstalk (FE_ctlk.tran) Far end Near end

25. 25 May 15 –Estimate the voltage bounce on Vdd and Vss pins of the core when it is mounted in a QFP 64. –The core clock is 20 MHz. Exercise 6. di/dt noise Core noise margin ? Ex4-didt_noise.sch

26. 26 May 15 Exercise 6. di/dt noise

27. 27 May 15 z11-dspic-vdd_10-vss_9.z Impedance vs. Freq Exercise 6. di/dt noise Inductance evaluation

28. 28 May 15 Typ min max R_pkg 19.05m 21.2m 16.9m L_pkg 3.025nH 2.61nH 3.44nH C_pkg 0.269pF 0.268pF 0.270pF Exercise 6. di/dt noise What IBIS Says ?

29. 29 May 15 Exercise 7. PDN Modeling DSPIC Z(f): find an R,L,C model Tune to measurement file: z11-dspic-vdd_10-vss_9.z Impedance vs. Freq

30. Exercise 7. PDN Modeling z11-C1nF_0603.z 1nF discrete capacitance for DPI 30 May 15 Impedance vs. Freq

31. 31 May 15 Synthesis of Exercises 1 to 7 What did we learn ?