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Link A/D converters and Microcontrollers using Long Transmission Lines John WU Precision Analog - Data Converter Applications Engineer

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Presentation on theme: "Link A/D converters and Microcontrollers using Long Transmission Lines John WU Precision Analog - Data Converter Applications Engineer"— Presentation transcript:

1 Link A/D converters and Microcontrollers using Long Transmission Lines John WU Precision Analog - Data Converter Applications Engineer wu_john@ti.com

2 Transmission Line Effect Considerations Definition of the Highest Frequency Signal Transmission Line Model Reflection Concept Termination Topology Crosstalk Analysis

3 Application Example

4 Transmitted Data and Clock

5 Reflection on MSP430

6 With Termination on MSP430

7 Reflection on ADS8326 EVM

8 With Termination on ADS8326 ?

9 Definition of the highest frequency signal What is the highest frequency signal in a 2.25MHz sample clock rate ADC ?

10 Definition of the highest frequency signal The highest frequency signal is determined by the signal rise or fall time

11 Rise Time vs. Bandwidth The rise time and bandwidth are related by: For example: clock rate = 2.25 MHz, t rise CLK = 10 ns t rise Data = 2 ns The highest frequency signal or bandwidth is: = 175MHz

12 Rise Time Measurement The displayed Tr = 2ns (10-90%) on an oscilloscope 3-dB bandwidth of a probe is 500MHz (Tr = 0.7ns) 3-dB bandwidth of an oscilloscope input is 350MHz (Tr=1ns) What is the measured input signal Tr ?

13 Rise Time Degradation T displayed 2 = T probe 2 + T scope 2 + T signal 2 T signal 2 = T displayed 2 -T probe 2 -T scope 2 T signal = SQRT(2 2 - 0.7 2 - 1 2 )=1.6ns! 1.6ns) = 220MHz

14 Critical Microstrip Length What is the critical length of a microstrip that must be considered as transmission line?

15 Rise Time vs. Propagation Delay

16 Propagation Delay vs. Dielectric Constant

17 Critical Microstrip Length Tr x 15% = 1.6ns x 15% = 226 ps = 1.5 inch

18 Transmission Line Model

19 Characteristic Impedance of Twisted Pair Cable & Microstrip

20 Reflection Factor If Z L >> Zo; Г = +1 If Z L << Zo; Г = -1 Zo Z L Г

21 S Parameters for Reflection

22 Reflection Analysis

23 Reflection Calculation

24 Calculated vs. Measured Reflection Tr/7

25 Critical Length of a Transmission Line What is the critical length of a transmission line that must be terminated?

26 Rise Time vs. Propagation Delay

27 Trace & Cable Terminations Source Termination Rt + Rs = Zo Receiver Rt Zo = 50  Driver Rs

28 Trace & Cable Terminations AC termination AC Termination

29 Place of Terminations Clock Source Clock Bus Termination Resistor Device 1Device 2 Stub Daisy Chain Routing with Stubs Device Pin BGA Ball

30 Short stubs create signal integrity problems Stub Length=0.5” Stub Length=0.25” Reference: Altera application note 224

31 Daisy Chain Routing without Stubs Clock Source Clock Bus Terminatio n Resistor Device Pin BGA Ball Device 1Device 2

32 Star Routing Clock Source Terminatio n Resistor Device 1 Device 2 Clock Bus Device Pin BGA Ball Device 3

33 Parallel Fly-By Termination Receiver Device (BGA Package) R2 Zo = 50  Vcc R1

34 Differential Pair (LVDS) Fly-By Termination Receiver Device (BGA Package) 100  Zo=50 

35 Crosstalk Analysis Cross Talk occurs on PCB and twisted wire cable

36 Magnetic & Electric Fields of Parallel Transmission Line Victim Trace Aggressor Trace Ground Plane Magnetic Field Aggressor Trace Victim Trace Electric Field Ground Plane

37 Cross Talk Analysis

38

39 FEXT Measurement Inductive or Capacitive Coupling ?

40 Reduced FEXT Measurement

41 NEXT Measurement

42 Reduced NEXT Measurement

43 Separated Data Wire

44 Cross Talk Reduced by Termination X- talk

45 Final Termination Solution

46 Conclusions The highest frequency signal is determined by switching time Transmission line model must be used when propagation delay time is greater than 15% of Tr Termination technique dramatically reduces reflection and crosstalk Q&A

47 Acknowledgement Thanks Phil Lizzi for providing the “real life” transmission line application example Reference: 1.“Managing Signal Quality” Mentor Graphics/Xilinx, 2005 http://www.xilinx.com/publications/xcellonline/xcell_53/xc_pdf/xc_mentor53.pdf 2.“High-Speed Board Layout Guideline” Altera application note 224, Sept. 2003


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