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01/25/2005 Combinationality of cyclic circuits EECS 290A – Spring 2005 UC Berkeley.

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Presentation on theme: "01/25/2005 Combinationality of cyclic circuits EECS 290A – Spring 2005 UC Berkeley."— Presentation transcript:

1 01/25/2005 Combinationality of cyclic circuits EECS 290A – Spring 2005 UC Berkeley

2 Outline Sequential circuits Synchronous vs. asynchronous Combinational circuits Definition Acyclic vs. cyclic circuits Cyclic circuits Origins and applications When cyclic circuits behave combinationally Up-bounded inertial delay model and ternary simulation Analysis and synthesis of cyclic circuits

3 Sequential circuits Synchronous vs. asynchronous implementations of finite state machines With/without reference clock Hybrid implementations (e.g. GALS, quasi delay- insensitive designs, de-synchronization, etc.) Strong/weak timing assumptions

4 Sequential circuits Sources of sequentiality (output valuation depends on input history) Feedback (cyclicity), or Delay

5 Combinational circuits Conceptual definition of combinational circuits For any input assignment, the output valuates to the same fixed value after a bounded amount of time Operational definition of combinational circuits Depending on timing and circuit (e.g. static CMOS, floating mode, etc.) model Here we use the up-bounded inertial (UIN) delay model [Brozowski & Seger 95] Ideal delay – glitches are persistent Inertial delay – small glitches are smoothed out

6 Up-bounded inertial delay model Up-bounded inertial delay model satisfies (0 <  (t) < D) 1. If z(t) changes from v to v’ at time t1, then there exists  > 0 such that x(t) = v’ for t1 –  ≤ t < t1. 2. If x(t) = v for t1 ≤ t < t1 + D, then there exists a time t2, t1 ≤ t2 < t1 + D such that z(t) = v for t2 ≤ t < t1 + D.

7 Combinationality and cyclicity Acyclic circuits are asymptotically combinational Circuits with delay elements without feedback are combinational in the asymptotic sense Cyclic circuits are not necessarily sequential or physically undesirable (e.g. oscillation, non- determinism, etc.) However, must be very careful in designing cyclic circuits

8 So cyclic combinational circuits? Why ? Possible area reduction for hardware (code-size reduction for software) Other advantages? Why not ? Sophisticated functional and timing analysis Still controversial

9 Early history about combinational cyclic circuits It is argued that, under some circumstances, cyclicity is a necessity to generate minimal combinational circuits [Kautz 70] This example is not good for all possible delay assignments [Shiple 96] 1 1 0 0 0

10 Early history about combinational cyclic circuits A more convincing family of examples [Rivest 77] The smallest acyclic implementation of the 2n output functions requires (3n – 2) two-fanin gates.

11 Recent interests in the EDA community Cyclic definitions occur commonly in high-level system designs [Stok 92] Not all cyclic dependencies are sequential or physically undesirable, e.g., z = if(c) then F(G(x)) else G(F(x)) More recently, make acyclic functions cyclic (to reduce area) [Riedel & Bruck 03]

12 Recent interests in the synchronous- language community Synchronous languages are popularly used in the design of real-time control systems Signals synchronized by global clock ticks Internal evaluations take zero time Instantaneous valuations of signals Esterel language allows simultaneous cyclic definitions of functional valuations Adopt the analysis of combinational cyclic circuits

13 Questions to be answered How to analyze if a cyclic circuit is “good” ? How to make cyclic circuits acyclic ? How to make acyclic circuits cyclic ?

14 Cyclic-circuit example 1 Combinational (Assume gates and wires can have arbitrary delays)

15 Cyclic-circuit example 2 Combinational but with internal oscillation (Assume gates and wires can have arbitrary delays)

16 Cyclic-circuit example 3 1 1 0 0 0 0 0 Not combinational even though functional analysis says so

17 When cyclic circuits behave combinationally Malik’s procedure [Malik 94] Select a cutset Perform ternary simulation Circuit is combinational iff, for any input assignment, each output valuates to either 0 or 1 after the simulation reaches a fixed point.

18 Ternary simulation Let “  ” denote the unknown value (the least element in the lattice with information partial order) Monotonicity is important for a fixed- point computation to guarantee termination Some examples F: {0,1,  } → {0,1,  }

19 Ternary simulation – example 1 Select a cutset, at (y,Y) say Let y have unknown value  Valuate all signals w.r.t. some input assignment

20 Ternary simulation – example 2 Not combinational

21 Ternary simulation – example 3 Combinational

22 Symbolic analysis For each signal s in the circuit, introduce two characteristic functions f s 0 (x) and f s 1 (x) such that f s 0 (x) = 1 iff input assignment x makes s valuates to 0 f s 1 (x) = 1 iff input assignment x makes s valuates to 1 Thus f s  (x) = ¬(f s 0 (x)  f s 1 (x) ) Ternary simulation are performed with symbolic computation Initially, PI variable x i has f x i 0 = ¬x i and f x i 1 = x i, and all other signals s has f s 0 = 0 and f s 1 = 0 In every iteration, simulate the acyclic circuit (due a cutset) in topological order from PI to PO with symbolic computation for each gate E.g., for w := AND(u,v), we have f w 0 = f u 0  f v 0 and f w 1 = f u 1  f v 1 From iteration t-1 to iteration t, update cutset f y 0[t] (x) := f Y 0[t -1] (x) and f y 0[t] (x) := f Y 0[t -1] (x) Simulation terminates when all cutset variable y has f y 0[t] (x) = f y 0[t -1] (x) and f y 1[t] (x) = f y 1[t -1] (x) Upon termination, the circuit is combinational iff every PO variable z i has f z i  = 0

23 Exactness of combinationality analysis Combinationality analysis using ternary simulation is exact under the UIN delay model [Shiple 96] However, UIN delay model might seem somewhat conservative (large glitches may be persistent) The analysis is also exact under up-bounded ideal delay model (?)

24 Complexity of combinationality analysis For any input assignment, ternary simulation converges in at most k iterations, where k is the cutset size Determining if a cyclic circuit is combinational is co-NP complete Find some input vector that makes the output behave non-deterministically

25 Making cyclic circuits acyclic Why? Most CAD algorithms do not support cyclic circuits (not separated by registers) To avoid complicated analysis and optimization How? In symbolic analysis, we get f z i 0 and f z i 1 for every primary output z i. By that, we know the function for z i, and can derive an acyclic implementation. [Malik 94], [Halbwachs & Maraninchi 95], [Edwards 03]

26 Other applications of combinationality analysis Constructive semantics in Esterel language Translate a program (with cyclic definitions) into a circuit netlist and then perform combinationality analysis

27 Synthesis of cyclic circuits Perform Boolean resubstitution as much as possible [Riedel & Bruck 03] Not restricted to the topological constraint of acyclicity Generalized Boolean resubstitution

28 Boolean resubstitution Given a Boolean function f, try to express f with another function g. E.g. f := abc + acd’ + abd g := a (b + d’) Rewriting f in terms of g yields f := (c + d) g Note that resubstitution is performed at the functional level

29 Synthesis of cyclic circuits Requirement Phrase the ternary simulation at the functional level: For every input assignment, there must be some signal valuating to either 0 or 1 such that all cyclic dependencies are broken

30 Synthesis of cyclic circuits The marginal operator [Riedel & Bruck 03] f  (x 1,…,x n )   x 1,…,x n. (f  x 1 )    (f  x n ) (f  x i )  f  x i =0 xnor f  x i =1 Condition C for a “network” N to be combinational C(N) = (f 1  I 1 )  C(N  f 1 )    (f k  I k )  C(N  f k ), where I i is the set of internal variables that f i depends upon (f i  I i ) denotes the condition where the valuation of f i is independent of the variables in I i N  f i denotes the subnetwork with every occurrence of f i substituted with its corresponding global function (or target function in [Riedel & Bruck 03]) in terms of PI variables

31 Cyclify acyclic functions – example 1 Consider network N 1 d  e = a + b’c’ e  f = c + ab’ f  d = b C(N 1  d ) = C(N 1  e ) = C(N 1  f ) = 1 C(N 1 ) = a + b’c’ + c + ab’ + b = 1 Global functions: d = c’(a’+b’) + a’b’ e = a’bc’ + b’(a+c) f = b’(a’+c’) + ab Cyclified functions: d = b’c’ + a’e e = b’(a+c) + c’f’ f = ab + b’d

32 Cyclify acyclic functions – example 2 Consider network N 2 Global functions: d = c’(a’+b’) + a’b’ e = a’bc’ + b’(a+c) f = b’(a’+c’) + ab Cyclified functions: d = b’f + c’e e = d(a+f’) + b’c f = ae’ + b’d d  (e,f) = bc e  (d,f) = b’c f  (d,e) = a’b C(N 2  d ) = 1 C(N 2  e ) = 0 C(N 2  f ) = b’ + c C(N 2 ) = bc (1) + b’c (0) + a’b (b’+c) = bc

33 Cyclify acyclic functions General procedure [Riedel & Bruck 03] Branch-and-bound algorithms Start from a “dense” cyclic network. Iteratively delete some dependency edges until the network is combinational. Start from a set of global functions. Iteratively perform resubstitution until combinationality cannot be maintained for any further resubstitution.

34 What’s missing? Purely functional analysis cannot guarantee well- behaved circuitry! [JMB 04] Non-functional restrictions need to be imposed. f := ¬a h  ¬b ¬h g := ¬a ¬b f h := a b  ¬g

35 Some possible non-functional restrictions Exclude axioms (x  ¬x) = true and (x  ¬x) = false from the marginal operator Add additional minterms f := ¬a h  ¬b ¬h  ¬a ¬b g := ¬a ¬b f h := a b  ¬g Other approaches ?

36 Timing analysis of cyclic circuits Topological longest paths may not be an adequate upper bound Following the ternary simulation procedure to determine longest paths False paths?

37 Summaries What we learned How to tell if a cyclic circuit is combinational How to make cyclic circuits acyclic How to synthesize cyclic circuits from acyclic functions What’s coming Software synthesis rather than hardware Combinationality at a higher abstraction level

38 References [Kautz 70] W. Kautz. The necessity of closed loops in minimal combinational circuits. IEEE Trans. On Computers, pp.162-164, Feb. 1970. [Rivest 77] R. Rivest. The necessity of feedback in minimal monotone combinational circuits. IEEE Trans. on Computers, pp.606-607, 1977. [Stok 92] L. Stok. False loops through resource sharing. In Proc. ICCAD, pp.345-348, 1992. [Malik 94] S. Malik. Analysis of cyclic combinational circuits. IEEE Trans. on CAD, pp.950-956, 1994. [Brozowski & Seger 95] J. Brozowski & C.-J. Seger. Asynchronous circuits. Springer-Verlag, 1995. [Halbwachs & Maraninchi 95] N. Halbwachs & F. Maraninchi. On the symbolic analysis of combinational loops in circuits and synchronous programs. In Proc. Euromicro, 1995. [Shiple 96] T. Shiple. Formal analysis of synchronous circuits. Ph.D. thesis, UCB, 1996. [Edwards 03] S. Edwards. Making cyclic circuits acyclic. In Proc. DAC, 2003. [Riedel & Bruck 03] M. Riedel & J. Bruck. The synthesis of cyclic combinational circuits. In Proc. DAC, 2003. Cyclic combinational circuits: analysis for synthesis. In Proc. IWLS, 2003. [JMB 04] On breakable cyclic definitions. In Proc. ICCAD, 2004.

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