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The Analysis of Cyclic Circuits with Boolean Satisfiability John Backes, Brian Fett, and Marc Riedel Electrical Engineering, University of Minnesota

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inputsoutputs The current outputs depend only on the current inputs. Combinational Circuits combinational logic

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x 0 0 0 a b c d AND OR AND OR x x 0 )))((( 1 fcdxab 1 f 0 Circuits with Cycles

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x 1 x 1 x x a b c d AND OR AND OR 1 1 1 )))((( 1 fcdab 1 f Circuits with Cycles

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1 1 x x x a b c d AND OR AND OR 1 ))((cdab 1 f )( 2 abxcdf Circuit is cyclic yet combinational; computes functions f 1 and f 2 with 6 gates. An acyclic circuit computing these functions requires 8 gates. Circuits with Cycles

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Circuit Model Perform analysis in the “floating-mode”. At the outset: all wires are assumed to have unknown/undefined values ( ). the primary inputs assume definite values in {0, 1}. a “controlling” input full set of “non-controlling” inputs unknown/undefined output

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Circuit Model During the analysis, we propagate controlling values. 1 ORAND Perform analysis in the “floating-mode”. At the outset: all wires are assigned to have unknown/undefined values ( ). the primary inputs assigned definite values in {0, 1}.

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Exhaustive Analysis Assign values to every wire Step through all primary inputs values Propagate all known values a b c d AND OR AND OR x x 1 1 1 1 0 0 0 1 1 1 1 0

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Exhaustive Analysis Assign values to every wire Step through all primary inputs values Propagate all known values a b c d AND OR AND OR x x 0 0 0 1 1 0 0 1 1 1 0 0

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Exhaustive Analysis Assign values to every wire Step through all primary inputs values Propagate all known values 1 1

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Previous Work S. Malik, Analysis of Cyclic Combinational Circuits. 1994 M. Riedel, J. Bruck, The Synthesis of Cyclic Combinational Circuits, DAC03: Design Automation Conference. 2003 Best Paper Award at DAC03 M. Riedel, J. Bruck, Timing Analysis of Cyclic Combinational Circuits.

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Analysis Combinational

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Analysis Not Combinational Analysis

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Why use Boolean Satisfiability (SAT)? BDD-based analysis is slow for large problem sizes SAT-based methods are known to be a good solution for large problem sizes in practice

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SAT-Based Analysis SAT-Based Analysis UNSAT (Combinational)

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SAT-Based Analysis SAT (Not Combinational) SAT-Based Analysis

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SAT Based Analysis of Cyclic Circuits Find feedback arc set Introduce dummy variables Encode the circuit computation for ternary- valued logic (0, 1, ) SAT Question: Is there any input assignment that produces values somewhere in the circuit? ┴ ┴

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Feedback and Dummy Variables

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Ternary Logic Conversion Ternary ANDEncoding SchemeBinary AND f 0 = a 0 b 0 + a 1 b 0 b 1 f 1 = a 1 b 1 + a 0 b 1 b 0

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The SAT Question “For any input assignment (where all dummy variables are assigned their correct values) does a value persist?” ┴

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1 1 Previous Example

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The Final SAT Instance

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Runtimes (seconds) CircuitAreaBDD BasedSAT BasedRatio 5xp12180.100.0110.00 bbara1350.01< 0.011.00 clip2920.090.019.00 cse3460.130.034.33 dk164260.090.033.00 duke26642.350.0733.57 ex15140.360.075.14 keyb4010.240.038.00 misex3106519.050.16119.00 planet8901.030.0812.88 planet18821.400.1112.73 pma3880.130.026.50 s15550.560.069.33 s148810361.430.1311.00 s3862240.02 1.00 sand8073.150.0745.00 average5521.880.0618.22

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Further Work Synthesis Implement new synthesis algorithm using Craig interpolation Builds off of algorithm proposed in: C.-C. Lee, J.-H. R. Jiang, C.-Y. Huang, and A. Mishchenko, “Scalable exploration of functional dependency by interpolation and incremental SAT solving”, ICCAD07: International Conference on Computer Aided Design. 2007.

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Further Work f 0 f 1 x 0 x 1...... x n f 2 f 3 f 0 f 1 f 2 f 3 x 0 x 1...... x n

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Acknowledgements Alan Mishchenko ABC: A System for Sequential Synthesis and Verification was used to along with MiniSat to implement the SAT Based algorithm Research funding was provided by FENA

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08/07/041 CSE-221 Digital Logic Design (DLD) Lecture-8:

08/07/041 CSE-221 Digital Logic Design (DLD) Lecture-8:

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