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The Analysis of Cyclic Circuits with Boolean Satisfiability John Backes, Brian Fett, and Marc Riedel Electrical Engineering, University of Minnesota.

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Presentation on theme: "The Analysis of Cyclic Circuits with Boolean Satisfiability John Backes, Brian Fett, and Marc Riedel Electrical Engineering, University of Minnesota."— Presentation transcript:

1 The Analysis of Cyclic Circuits with Boolean Satisfiability John Backes, Brian Fett, and Marc Riedel Electrical Engineering, University of Minnesota

2 inputsoutputs The current outputs depend only on the current inputs. Combinational Circuits combinational logic

3 x a b c d AND OR AND OR x x 0 )))((( 1 fcdxab 1 f  0 Circuits with Cycles

4 x 1 x 1 x x a b c d AND OR AND OR )))((( 1 fcdab 1 f  Circuits with Cycles

5 1 1 x x x a b c d AND OR AND OR 1 ))((cdab 1 f  )( 2 abxcdf  Circuit is cyclic yet combinational; computes functions f 1 and f 2 with 6 gates. An acyclic circuit computing these functions requires 8 gates. Circuits with Cycles

6 Circuit Model Perform analysis in the “floating-mode”. At the outset: all wires are assumed to have unknown/undefined values ( ). the primary inputs assume definite values in {0, 1}. a “controlling” input full set of “non-controlling” inputs unknown/undefined output

7 Circuit Model During the analysis, we propagate controlling values. 1    ORAND   Perform analysis in the “floating-mode”. At the outset: all wires are assigned to have unknown/undefined values ( ). the primary inputs assigned definite values in {0, 1}.

8 Exhaustive Analysis Assign values to every wire Step through all primary inputs values Propagate all known values a b c d AND OR AND OR x x

9 Exhaustive Analysis Assign values to every wire Step through all primary inputs values Propagate all known values a b c d AND OR AND OR x x

10 Exhaustive Analysis Assign values to every wire Step through all primary inputs values Propagate all known values 1 1

11 Previous Work S. Malik, Analysis of Cyclic Combinational Circuits M. Riedel, J. Bruck, The Synthesis of Cyclic Combinational Circuits, DAC03: Design Automation Conference  Best Paper Award at DAC03 M. Riedel, J. Bruck, Timing Analysis of Cyclic Combinational Circuits.

12 Analysis Combinational

13 Analysis Not Combinational Analysis

14 Why use Boolean Satisfiability (SAT)? BDD-based analysis is slow for large problem sizes SAT-based methods are known to be a good solution for large problem sizes in practice

15 SAT-Based Analysis SAT-Based Analysis UNSAT (Combinational)

16 SAT-Based Analysis SAT (Not Combinational) SAT-Based Analysis

17 SAT Based Analysis of Cyclic Circuits Find feedback arc set Introduce dummy variables Encode the circuit computation for ternary- valued logic (0, 1, ) SAT Question: Is there any input assignment that produces values somewhere in the circuit? ┴ ┴

18 Feedback and Dummy Variables

19 Ternary Logic Conversion Ternary ANDEncoding SchemeBinary AND f 0 = a 0 b 0 + a 1 b 0 b 1 f 1 = a 1 b 1 + a 0 b 1 b 0

20 The SAT Question “For any input assignment (where all dummy variables are assigned their correct values) does a value persist?” ┴

21 1 1 Previous Example

22 The Final SAT Instance

23

24 Runtimes (seconds) CircuitAreaBDD BasedSAT BasedRatio 5xp bbara < clip cse dk duke ex keyb misex planet planet pma s s s sand average

25 Further Work Synthesis  Implement new synthesis algorithm using Craig interpolation  Builds off of algorithm proposed in: C.-C. Lee, J.-H. R. Jiang, C.-Y. Huang, and A. Mishchenko, “Scalable exploration of functional dependency by interpolation and incremental SAT solving”, ICCAD07: International Conference on Computer Aided Design

26 Further Work f 0 f 1 x 0 x x n f 2 f 3 f 0 f 1 f 2 f 3 x 0 x x n

27 Acknowledgements Alan Mishchenko ABC: A System for Sequential Synthesis and Verification was used to along with MiniSat to implement the SAT Based algorithm Research funding was provided by FENA


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