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Device: WP2 Interface & materials Amit K. Tiwari, Nick Wright and Anthony O’Neill School of Electrical and Electronic Engineering Newcastle University.

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Presentation on theme: "Device: WP2 Interface & materials Amit K. Tiwari, Nick Wright and Anthony O’Neill School of Electrical and Electronic Engineering Newcastle University."— Presentation transcript:

1 Device: WP2 Interface & materials Amit K. Tiwari, Nick Wright and Anthony O’Neill School of Electrical and Electronic Engineering Newcastle University

2 Hot spot 1.Designing, parameter optimisation and performance evaluations of power semiconductor devices 1 (static, transient, electro-thermal, breakdown analyses) Transient analysis Self-heating analysis Our research work area Breakdown Contd... Lateral JFET Vertical JFET Breakdown-analysis 1. High voltage 4H-SiC current limiting device for serial protection applications, submitted to ECSCRM Design optimization and performance evaluation of a 10 kV super- junction power SiC-JFET, submitted to ECSCRM Self-heating effects in lateral JFETs, in preparation for IEEE TED.

3 Contd Device fabrication and characterisation V ov =V gs -V T SEM image of cross-section of a lateral FET 1. Manuscript in preparation

4 3. Modelling of wide bandgap materials (SiC and diamond) and surface/interfaces analysis (a) Surface topography and (b) contact potential difference (Kelvin probe measurement) map for a nano-crystalline diamond surface 4H-SiC (C-face) 4H-SiC (Si-face) [001] Oriented metal terminated diamond surface Electronic affinity calculation for H- and O-terminated diamond surfaces 1.Electronic and structural properties of diamond (100) surfaces terminated by selected transition metals, PRB Calculated electron affinity and stability of halogen-terminated diamond, PRB Tuning optoelectronic properties of 4H-SiC QDs using -H, -OH and -F surface functionalisation, submitted to ECSCRM2014.

5 Project Plans & Objectives L n L p L n =L p Super-junction VJFET structure Designing and performance evaluation of novel high temperature and high voltage SiC devices for rugged electronic applications (our current main focus is on the super-junction structures) Development of fabrication process steps and high temperature device packaging analysis for thermal management Extreme environments testing Charge-imbalence analysis 1. Design optimization and performance evaluation of high voltage (>1 kV) super–junction SiC–JFETs, in preparation for IEEE TED.

6 Potential Outcomes & Exploitation Plans Outcomes: Commercially unavailable novel high temperature and high voltage SiC-devices Advancement of underpinning material growth and device fabrication technology Exploitation: Technology dissemination to the wider power-electronics community working in different areas (aerospace, automobile and power distribution sectors) through the knowledge transfer networks and potential collaborations. Publications in refereed academic journals and conferences, and feature articles in trade journals

7 Input from the PE Community Any experience/feedback regarding the super-junction and electro-thermal simulations of thick device (several 100s microns) structures will be much appreciated.

8 Thanks


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