1. ECE-C 302 Lecture Data Storage Prawat Nagvajara Stack: Last-in First-out (LIFO) Queue: First-in First-out (FIFO) Random Access Memory

2. Stack or Last-in First-out (LIFO) Stack Base = 0xFFFF Location (Address) 0xFFE7 0xFFE8 0xFFE9 0xFFFA 0xFFFB 0xFFFC 0xFFFD 0xFFFE 0xFFFF Top-of-Stack Pointer

3. After 5 pops and a push Location (Address) 0xFFE7 0xFFE8 0xFFE9 0xFFFA 0xFFFB 0xFFFC 0xFFFD 0xFFFE 0xFFFF Top-of-Stack Pointer

4. FIFO Initially the FIFO is empty Location 0 1 2 3 4 5 6 7 0 (end around) Front Ptr Rear Ptr

5. After a Write Location 0 1 2 3 4 5 6 7 0 (end around) Front Ptr Rear Ptr

6. After three more Writes Location 0 1 2 3 4 5 6 7 0 (end around) Front Ptr Rear Ptr

7. After Two Reads Location 0 1 2 3 4 5 6 7 0 (end around) Front Ptr Rear Ptr

8. And Two More Reads The Queue is Empty (Front = Rear) Location 0 1 2 3 4 5 6 7 0 (end around) Front Ptr Rear Ptr

9. After Eight Writes The Queue is Full (Rear = Front) Location 0 1 2 3 4 5 6 7 0 (end around) Front Ptr Rear Ptr

10. Random Access Memory Array of byte or word –Demultiplex when write –Multiplex when read SRAM –Instantiation –Used for implementation of embedded FIFO and stack DRAM modulo with asynchronous read and write

11. Stack and Queue Codes package s_pack is type integer_array is array (natural range <>) of integer; type op_type is (push, pop, no_operation); end s_pack; library ieee; Use ieee.std_logic_1164.all,work.s_pack.all; entity stack is generic (d: natural := 256); Port (x: in integer; y: out integer; sel: in op_type; ck: in std_logic); end stack;

12. -- DESCRIPTION -- *********** -- * A stack is a storage of at most d integers.It is -- last-in first-out data storage similar to a cafeterial -- stack of trays, where data are the trays. -- * The output port y is connected to the top-of-stack (TOS). -- * When a pop operation is selected, the integer stored before -- the top-of-stack becomes the new top-of-stack. -- * When a push operation is selected, the input is stored into -- the top-of-stack and the previous data are pushed down. -- * The transfer of data happens on the clock rising edge. -- * The no_operation select means no datum is transferred.

13. -- -- TOS -- ----------------- -- x ---->| | |... | | -- y <----| | |... | | -- ----------------- -- storage -- -- Code a behavioral architecture architecture behav of stack is -- internal signal signal storage:integer_array(1 to d);

14. begin process(ck) begin if ck = '1' then case sel is when push => storage(1) <= x; for i in 1 to d-1 loop storage(i+1) <= storage(i); end loop;

15. when pop => for i in 1 to d-1 loop storage(i) <= storage(i+1); end loop; when no_operation => null; end case; end if; end process; y <= storage(1); end behav;

17. Stack (Last-in First-out, LIFO) Stack design example in Bhasker text p. 273 Uses the for generate construct to create array of registers Use component reg8 G1: For k in 1 to N generate G2: if k = N generate -- top regin 1 and k ‘U’); end generate G4; FF8: Reg8 port map (regin, data(k), ck); End generate G1; Dataout <= data(N);

18. --First-in first-out queue package FIFO_pack is type integer_array is array (natural range <>) of integer; type op_type is (push, pop, no_operation); end FIFO_pack; library ieee; Use ieee.std_logic_1164.all,work.FIFO_pack.all; entity FIFO is generic (d: natural := 5); port ( x : in integer; y : out integer; select_operation : in op_type; ck : in std_logic); end FIFO;

19. DESCRIPTION * First-In First-Out is a queue - a storage of integers. Operations consist of push, pop and no operation. When pop, the integer that had been first stored is assigned to y and it will be trashed and, an addition storage space is available. When push, an integer at port x is stored. * EMPTY and FULL conditions: if the queue is full or empty, an assert statement will be used to indicate the condition when a user try to push or pop, respectively.

20. architecture behav of FIFO is -- internal signal signal storage : integer_array(1 to d); type state_type is (empty, has_data, full); begin process(ck) variable fp, rp : integer := 1; --front and rear pointers variable q_state : state_type := empty; begin if ck=‘1’ then case select_operation is when no_operation => null;

21. when push => case q_state is when empty => storage(rp) <= x; if rp = d then rp := 1; else rp := rp+1; end if;--increment w/ end around q_state := has_data; when has_data => storage(rp) <= x; if rp = d then rp := 1; else rp := rp+1; end if;--increment w/ end around if rp = fp then q_state := full; end if; when full => assert false report "QUEUE FULL" severity ERROR; end case;

22. when pop => case q_state is when empty => assert false report "QUEUE EMPTY" severity ERROR; when has_data => y <= storage(fp); if fp = d then fp := 1; else fp := fp+1; end if;--increment w/ end around if fp = rp then q_state := empty; end if; when full => y <= storage(fp); if fp = d then fp := 1; Else fp := fp+1; end if;--increment w/ end around q_state := has_data; end case; end if; end process; end behav;

23. RAM -- Single port Block RAM entity spblockram is port (clk : in std_logic; we : in std_logic; a : in std_logic_vector(4 downto 0); di : in std_logic_vector(3 downto 0); do : out std_logic_vector(3 downto 0)); end spblockram; architecture syn of spblockram is type ram_type is array (31 downto 0) of std_logic_vector (3 downto 0); signal RAM : ram_type; signal read_a : std_logic_vector(4 downto 0); begin process (clk) begin if (clk'event and clk = '1') then if (we = '1') then RAM(conv_integer(a)) <= di; end if; read_a <= a; end if; end process;