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Gheorghe M. Ştefan http://arh.pub.ro/gstefan/ - 2014 -

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3-Loop Digital Systems: Processors Digital Integrated Circuits - week eleven2

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Automata with “intelligent registers” DF-F JKF-F 0 -> 0 0 00 or 01 : 0- 0 -> 1 1 10 or 11 : 1- 1 -> 0 0 01 or 11 : -1 1 -> 1 1 00 or 10 : -0 0 -> A A : A- 1 -> A A : -A’ Digital Integrated Circuits - week eleven3

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The complex part of the circuit is reduced. Sometimes, the weight of the simple part increase. S DF-F / S JKF-F = ? Digital Integrated Circuits - week eleven5

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Comments on autonomy Why the complex part is reduced? Because each new loop closed in the system increases the autonomous behavior: The first loop provides the autonomy of the state Te second loop provides the autonomy to evolve What kind of autonomy provides the third loop? Digital Integrated Circuits - week eleven6

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Loop closed through memory Digital Integrated Circuits - week eleven7

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9 The third loop simplified the sequencer: instead of a control automaton a command automaton is used.

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Loop-coupled automata Maximal segregation between simple structure and complex structure Def.: Processor = loop-coupled a simple functional automaton with a complex control automaton. Def.: Elementary processor = the control automaton execute only one control sequence. Digital Integrated Circuits - week eleven10

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Pixel correction revisited Digital Integrated Circuits - week eleven11

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The control automaton Digital Integrated Circuits - week eleven12

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Processor Composes & loops functions performed by elementary processors Elementary computations = instructions Instead of composing circuits, are composed instructions = compositions in the symbolic domain Instruction set architecture (ISA): is an interface Performing instructions: execute in one cycle interpret expanding in a sequence Digital Integrated Circuits - week eleven13

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Digital Integrated Circuits - week eleven14

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Harvard vs. von Neumann abstract model (architecture) Harvard von Neumann abstract model abstract model Digital Integrated Circuits - week eleven15

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An executing processor: RISC Digital Integrated Circuits - week eleven16

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RISC: Reduced Instruction Set Computer Each instruction is executed in one clock cycle ISA includes only the most frequently used instructions Any complex instruction results as a sequence of RISC instructions Digital Integrated Circuits - week eleven17

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Digital Integrated Circuits - week eleven18

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External connections Data memory & Program memory are directly connected only for simplicity. The good practices request pipelined of fully buffered connections. Digital Integrated Circuits - week eleven19

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Digital Integrated Circuits - week eleven20

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Digital Integrated Circuits - week eleven21

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Digital Integrated Circuits - week eleven22

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Facultative home work Problema 1: proiectai automatul finit din slide-ul Pixel correction revisited (slide 11). Sinteză plus simulare. Problema 2: proiectai sectiunea Control a procesorului toyRISC (vezi slide 16 si slide 21). Sinteză plus simulare. Digital Integrated Circuits - week eleven23

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