Download presentation

Presentation is loading. Please wait.

1
Gheorghe M. Ştefan

2
3-Loop Digital Systems: Processors Digital Integrated Circuits - week eleven2

3
Automata with “intelligent registers” DF-F JKF-F 0 -> or 01 : > or 11 : > or 11 : > or 10 : > A A : A- 1 -> A A : -A’ Digital Integrated Circuits - week eleven3

4
4

5
The complex part of the circuit is reduced. Sometimes, the weight of the simple part increase. S DF-F / S JKF-F = ? Digital Integrated Circuits - week eleven5

6
Comments on autonomy Why the complex part is reduced? Because each new loop closed in the system increases the autonomous behavior: The first loop provides the autonomy of the state Te second loop provides the autonomy to evolve What kind of autonomy provides the third loop? Digital Integrated Circuits - week eleven6

7
Loop closed through memory Digital Integrated Circuits - week eleven7

8
8

9
9 The third loop simplified the sequencer: instead of a control automaton a command automaton is used.

10
Loop-coupled automata Maximal segregation between simple structure and complex structure Def.: Processor = loop-coupled a simple functional automaton with a complex control automaton. Def.: Elementary processor = the control automaton execute only one control sequence. Digital Integrated Circuits - week eleven10

11
Pixel correction revisited Digital Integrated Circuits - week eleven11

12
The control automaton Digital Integrated Circuits - week eleven12

13
Processor Composes & loops functions performed by elementary processors Elementary computations = instructions Instead of composing circuits, are composed instructions = compositions in the symbolic domain Instruction set architecture (ISA): is an interface Performing instructions: execute in one cycle interpret expanding in a sequence Digital Integrated Circuits - week eleven13

14
Digital Integrated Circuits - week eleven14

15
Harvard vs. von Neumann abstract model (architecture) Harvard von Neumann abstract model abstract model Digital Integrated Circuits - week eleven15

16
An executing processor: RISC Digital Integrated Circuits - week eleven16

17
RISC: Reduced Instruction Set Computer Each instruction is executed in one clock cycle ISA includes only the most frequently used instructions Any complex instruction results as a sequence of RISC instructions Digital Integrated Circuits - week eleven17

18
Digital Integrated Circuits - week eleven18

19
External connections Data memory & Program memory are directly connected only for simplicity. The good practices request pipelined of fully buffered connections. Digital Integrated Circuits - week eleven19

20
Digital Integrated Circuits - week eleven20

21
Digital Integrated Circuits - week eleven21

22
Digital Integrated Circuits - week eleven22

23
Facultative home work Problema 1: proiectai automatul finit din slide-ul Pixel correction revisited (slide 11). Sinteză plus simulare. Problema 2: proiectai sectiunea Control a procesorului toyRISC (vezi slide 16 si slide 21). Sinteză plus simulare. Digital Integrated Circuits - week eleven23

Similar presentations

© 2016 SlidePlayer.com Inc.

All rights reserved.

Ads by Google