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Net-Ordering for Optimal Circuit Timing in Nanometer Interconnect Design M. Sc. work by Moiseev Konstantin Supervisors: Dr. Shmuel Wimer, Dr. Avinoam Kolodny

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Problem formulation Minimize bus timing by ordering of wires and allocation of wire widths and inter-wire spaces Minimize bus timing by ordering of wires and allocation of wire widths and inter-wire spaces Total width of interconnect structure is given constant A Total width of interconnect structure is given constant A All wires have equal length L All wires have equal length L A L W i-1 WiWi W i+1 SiSi S i+1 R i-1 RiRi R i+1 C i-1 CiCi C i+1 V cc

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Motivation Cross-capacitances between wires in interconnect structures have a major effect on circuit timing Cross-capacitances between wires in interconnect structures have a major effect on circuit timing Wires 10 years ago – area capacitance was dominant Wires today – cross capacitance is dominant

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Motivation Relative order of wire drivers in a bus influences circuit timing Relative order of wire drivers in a bus influences circuit timing Case ACase B Weak driver Strong driver Capacitive load Circuit timing is better in case B !

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Previous work Bus design: Bus design: A. Kahng, S. Muddu, E. Sarto and R. Sharma, 1998 A. Kahng, S. Muddu, E. Sarto and R. Sharma, 1998 T. Lin and L. Pillegi, 2002 – another approach T. Lin and L. Pillegi, 2002 – another approach Sizing and spacing multiple nets with consideration of coupling capacitance Sizing and spacing multiple nets with consideration of coupling capacitance J. Cong, L. He, C. Koh and Z. Pan, 2001 J. Cong, L. He, C. Koh and Z. Pan, 2001 Wire ordering for area minimization Wire ordering for area minimization Groeneveld, 1989 and other old works Groeneveld, 1989 and other old works Wire ordering for noise minimization Wire ordering for noise minimization Many works: Kirkpatrik, Vitall, Gao, Gupta etc. ( ) Many works: Kirkpatrik, Vitall, Gao, Gupta etc. ( ) Wire ordering for power minimization Wire ordering for power minimization Macii, Poncino & Salerno, 2003 Macii, Poncino & Salerno, 2003 Wire ordering for delay minimization Wire ordering for delay minimization None ! None ! It ’ s our goal

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Delay model Elmore approximation for delay together with - model equivalent circuit for wire Elmore approximation for delay together with - model equivalent circuit for wire Q: Is Elmore delay model good enough for state-of-the-art technology? A: Fitted Elmore Delay model gives up to 2% error in delay estimation Miller factor assumed 1 for all wires Miller factor assumed 1 for all wires More general case will be discussed later More general case will be discussed later

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Objective functions Total sum of delays: Worst wire delay: Worst wire slack:

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Environment conditions Wire environment conditions are defined by pair Wire environment conditions are defined by pair (or triple in case of minimum slack optimization) (or triple in case of minimum slack optimization) All other terms encapsulate wire intrinsic parameters All other terms encapsulate wire intrinsic parameters Ordering optimization is performed according to wires ’ environment conditions, followed by optimization on intrinsic parameters Ordering optimization is performed according to wires ’ environment conditions, followed by optimization on intrinsic parameters Another form of expressing wire delay:

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Solution flow Assume ordering of wires is given Solve wire-sizing – inter-wire space optimization problem for given ordering (previous work) (previous work) Obtain relations between intrinsic parameters and environmental conditions for this solution Find wire ordering (according to environment conditions) minimizing the solution

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Agenda Solution for total sum of delays objective function Solution for total sum of delays objective function Solution for worst delay objective function Solution for worst delay objective function Optimization of total sum of delays with cross talk Optimization of total sum of delays with cross talk Delay uncertainty issue Delay uncertainty issue

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Solution for total sum of delays case constant wire width Differentiating function with respect to and area constraint and equating derivatives to zero, obtain: Differentiating function with respect to and area constraint and equating derivatives to zero, obtain: Now assume all wires have predefined constant width and get: Now assume all wires have predefined constant width and get: This property is preserved in all kinds of optimizations discussed

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Solution for total sum of delays case constant wire width Substitute obtained relations for spaces to objective function, simplify and obtain: Substitute obtained relations for spaces to objective function, simplify and obtain: Order-independent part Order-dependent part Order of wires is influenced by values of driver resistances only ! Question: Does optimal order exist ???

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BMI order Take wires sorted in descending order of drivers and put alternately to the left and right sides of the bus channel Take wires sorted in descending order of drivers and put alternately to the left and right sides of the bus channel Obtained permutation of wires called Balanced Monotonic Interleaved (BMI) order Obtained permutation of wires called Balanced Monotonic Interleaved (BMI) order BMI order BMI order provides best sharing of inter-wire spaces

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Optimal order theorem Define, where - non-decreasing monotonic function and - some permutation of -values Define, where - non-decreasing monotonic function and - some permutation of -values Theorem (optimal order): given a bus whose wires are of uniform width, the BMI order of signals in the bus yields minimum total sum of delays. Theorem (optimal order): given a bus whose wires are of uniform width, the BMI order of signals in the bus yields minimum total sum of delays. Proof : Proof : Order-dependent part of is special case of -sum Order-dependent part of is special case of -sum Prove by induction that -sums are minimized by BMI permutation Prove by induction that -sums are minimized by BMI permutation

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Impedance matching Balance the resistance of the driver and resistance of the driven line Balance the resistance of the driver and resistance of the driven line Mathematically: Mathematically: BMI still holds BMI still holds Simple but practical case: Simple but practical case:

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Solution for general case In general case, wire widths are optimization variables In general case, wire widths are optimization variables Derivatives with respect to : Derivatives with respect to : Theorem (existence): For given set of wires, if for each pair of wires and with drivers and loads and respectively holds and, then optimal order of this set of wires is BMI, under total sum of wire delays objective function. Theorem (existence): For given set of wires, if for each pair of wires and with drivers and loads and respectively holds and, then optimal order of this set of wires is BMI, under total sum of wire delays objective function. One special case: if all load capacitances are equal, then optimal order is always BMI One special case: if all load capacitances are equal, then optimal order is always BMI

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Minimizing total sum of delays - summary 1. Generate all permutations of wires 2. For each permutation solve sizing problem 3. Find permutation giving minimum delay Complexity: exponential Complexity: exponential Number of optimization variables: Number of optimization variables: 1. Generate all permutations of wires 2. For each permutation solve sizing problem 3. Find permutation giving minimum delay Complexity: exponential Complexity: exponential Number of optimization variables: Number of optimization variables: 1. Perform impedance matching by function with parameters (if needed) 2. Arrange wires in BMI order 3. Solve sizing problem Complexity: linear Number of optimization variables: or 1. Perform impedance matching by function with parameters (if needed) 2. Arrange wires in BMI order 3. Solve sizing problem Complexity: linear Number of optimization variables: or Our heuristic: Straight forward solution :

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Results: total sum minimization problem demonstration on random problem instances 20 sets of 5 wires 20 sets of 5 wires R dr : [0.1 ÷ 2] KΩ R dr : [0.1 ÷ 2] KΩ(random) C l : [10 ÷ 200] fF C l : [10 ÷ 200] fF(random) Bus length: 600 μm Bus length: 600 μm Bus width: 12 μm Bus width: 12 μm Technology: 90 nm Technology: 90 nm

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Results: total sum minimization bus width influence Set of 6 wires Set of 6 wires R dr : [0.1 ÷ 2] KΩ R dr : [0.1 ÷ 2] KΩ(random) C l : 10 fF C l : 10 fF Bus length: 600 μm Bus length: 600 μm Technology: 90 nm Technology: 90 nm Diff., % Worst delay obtained Best delay obtained Bus width, [ μ m]

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Results: total sum minimization interleaved bus Diff., % Worst delay obtained, [ps] Best delay obtained, [ps] No. of weak drivers Set of 7 wires Set of 7 wires R dr : 0.1KΩ and 1.9 KΩ R dr : 0.1KΩ and 1.9 KΩ C l : 50 fF and 5 fF C l : 50 fF and 5 fF Bus length: 600 μm Bus length: 600 μm Bus width: 15 μm Bus width: 15 μm Technology: 90 nm Technology: 90 nm

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Results: total sum minimization comparison of heuristics on random problem instances Exhaustive search best delay Exhaustive search worst delay 0.63% 0.76% 0.63% 0.07% 0.21% 0.20% 16.54% 12.60% 16.39% 11.28% 14.10% 9.60% Average: 0.42%14.10% 1 st heuristic 2 nd heuristic 100%

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Results: total sum minimization comparison of heuristics on random problem instances Sets of 5 wires; same bus characteristics as earlier Sets of 5 wires; same bus characteristics as earlier Parametric width opt.Uniform width opt. Exhaustive search worst delay, [ps] Exhaustive search best delay, [ps] % Num. value, [ps] % Average:

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Agenda Solution for total sum of delays objective function Solution for total sum of delays objective function Solution for worst delay objective function Solution for worst delay objective function Optimization of total sum of delays with cross talk Optimization of total sum of delays with cross talk Delay uncertainty issue Delay uncertainty issue

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Solution for minmax case The goal: minimizing maximum wire delay (or slack) The goal: minimizing maximum wire delay (or slack) Function is not differentiable Function is not differentiable All wires have the same delay (S. Michaely et al.) All wires have the same delay (S. Michaely et al.) Assumptions: Assumptions: wire width is convex monotonic decreasing in driver resistance (impedance matching) wire width is convex monotonic decreasing in driver resistance (impedance matching) Drivers and loads satisfy existence theorem Drivers and loads satisfy existence theorem

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Solution for minmax case Supposition: In minimization of maximum wire delay, optimal order of wires is BMI Supposition: In minimization of maximum wire delay, optimal order of wires is BMI Under assumptions of previous slide delay expression can be written as: Under assumptions of previous slide delay expression can be written as: Edge effects (S. Michaely et. al) can break down optimality of BMI Edge effects (S. Michaely et. al) can break down optimality of BMI

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Influence of edge effects When variance of driver resistances is small, values of are defined by edge effects When variance of driver resistances is small, values of are defined by edge effects Delay is minimized by placing drivers in ABMI (anti BMI) order Delay is minimized by placing drivers in ABMI (anti BMI) order Figure 13. Distribution of wire widths and inter-wire spaces after minmax delay optimization Figure 14. Placement of wires influenced by edge effects in minmax optimization

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Results: minmax optimization bus width influence 20 sets of 5 wires 20 sets of 5 wires R dr : [0.1 ÷ 2] KΩ R dr : [0.1 ÷ 2] KΩ(random) C l : [10 ÷ 200] fF C l : [10 ÷ 200] fF(random) Bus length: 600 μm Bus length: 600 μm Technology: 90 nm Technology: 90 nm Obtained optimization impact, percent Bus width, um

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Results: minmax optimization bus length influence 20 sets of 5 wires 20 sets of 5 wires R dr : [0.1 ÷ 2] KΩ R dr : [0.1 ÷ 2] KΩ(random) C l : [10 ÷ 200] fF C l : [10 ÷ 200] fF(random) Bus width: 12 μm Bus width: 12 μm Technology: 90 nm Technology: 90 nm Obtained optimization impact, percent Bus length, μ m

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Results: minmax optimization interleaved bus Diff., % Worst delay obtained, [ps] Best delay obtained, [ps] No. of weak drivers Set of 7 wires Set of 7 wires R dr : 0.1KΩ and 1.9 KΩ R dr : 0.1KΩ and 1.9 KΩ C l : 50 fF and 5 fF C l : 50 fF and 5 fF Bus length: 600 μm Bus length: 600 μm Bus width: 15 μm Bus width: 15 μm Technology: 90 nm Technology: 90 nm

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Agenda Solution for total sum of delays objective function Solution for total sum of delays objective function Solution for worst delay objective function Solution for worst delay objective function Optimization of total sum of delays with cross talk Optimization of total sum of delays with cross talk Delay uncertainty issue Delay uncertainty issue

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Crosstalk issue So far: we assumed Miller factor 1 So far: we assumed Miller factor 1 In practice: can be 0, 1 or 2 In practice: can be 0, 1 or 2 Introducing Miller factor changes wire delay equation: Introducing Miller factor changes wire delay equation: The solution will be different according to three cases: The solution will be different according to three cases: Miller factor is equal for all pairs of wires Miller factor is equal for all pairs of wires Miller factor different only near walls Miller factor different only near walls Each pair of wires has its own different Miller factor Each pair of wires has its own different Miller factor

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1 st case: uniform Miller factor The order-dependent part of objective function is given as: The order-dependent part of objective function is given as: When all Miller coefficients are equal, above expression changes to: When all Miller coefficients are equal, above expression changes to: Conclusion: Conclusion: Uniform Miller factor doesn’t affect functional form of delay function and therefore optimal order will be BMI Uniform Miller factor doesn’t affect functional form of delay function and therefore optimal order will be BMI Impact of wire ordering emphasized even more Impact of wire ordering emphasized even more

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2 nd case: almost uniform Miller factor All Miller coefficients in internal inter-wire spaces are equal to All Miller coefficients in internal inter-wire spaces are equal to Miller coefficients near the walls are Miller coefficients near the walls are Order-dependent part of objective function can be written as: Order-dependent part of objective function can be written as: BMI order remains optimal if BMI order remains optimal if In other cases order is monotonic but not always BMI In other cases order is monotonic but not always BMI Minmax optimization gives the same results Minmax optimization gives the same results

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3 rd case: non-uniform Miller factor Miller coefficients can be presented by the matrix Minimization problem then is equivalent to : Where and Proved to be NP-complete (A. Vittal et al.) Proved to be NP-complete (A. Vittal et al.)

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Agenda Solution for total sum of delays objective function Solution for total sum of delays objective function Solution for worst delay objective function Solution for worst delay objective function Optimization of total sum of delays with cross talk Optimization of total sum of delays with cross talk Delay uncertainty issue Delay uncertainty issue

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Delay uncertainty issue Due to difference in arrival times of signals transmitted by neighbor wires, crosstalk noise is created Due to difference in arrival times of signals transmitted by neighbor wires, crosstalk noise is created Crosstalk noise is characterized by two main parameters: peak noise and delay uncertainty Crosstalk noise is characterized by two main parameters: peak noise and delay uncertainty Peak noise Delay uncertainty Maximum delay uncertainty for a signal in a bus can be expressed as follows: Maximum delay uncertainty for a signal in a bus can be expressed as follows: (A. Vittal et al., T. Sato et al.)

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Minimization of delay uncertainty Define new objective functions: Define new objective functions: Total sum of delay uncertainties: Total sum of delay uncertainties: Worst delay uncertainty : Worst delay uncertainty : Experiments show that BMI order leads to minimizing both and Experiments show that BMI order leads to minimizing both and

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Results: minimization of delay uncertainty 20 sets of 5 wires 20 sets of 5 wires R dr : [0.1 ÷ 2] KΩ R dr : [0.1 ÷ 2] KΩ(random) C l : [10 ÷ 200] fF C l : [10 ÷ 200] fF(random) Bus length: 600 μm Bus length: 600 μm Bus width: 15 μm Bus width: 15 μm Technology: 90 nm Technology: 90 nm Total sum Minmax Average improvement: Average improvement: Total sum of delay uncertainties: about 27 % Total sum of delay uncertainties: about 27 % Worst delay uncertainty: Worst delay uncertainty: about 43% about 43%

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Monotony in ordering optimizations Monotony is most important property of solutions of ordering optimization problems Monotony is most important property of solutions of ordering optimization problems Total sum of delays: optimal order is monotonic, BMI Total sum of delays: optimal order is monotonic, BMI Maximum delay: optimal order is monotonic, BMI Maximum delay: optimal order is monotonic, BMI Optimization with crosstalk: optimal order is monotonic Optimization with crosstalk: optimal order is monotonic Delay uncertainty optimization: optimal order is monotonic, BMI Delay uncertainty optimization: optimal order is monotonic, BMI Generally, all above problems can be solved on cyclic bus and obtained optimal order will be monotonic Generally, all above problems can be solved on cyclic bus and obtained optimal order will be monotonic BMI and other monotonic orders are special cases and defined by edge conditions only BMI and other monotonic orders are special cases and defined by edge conditions only

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Conclusions Problem of optimal simultaneous wire sizing and ordering was presented and solved Problem of optimal simultaneous wire sizing and ordering was presented and solved Effects of crosstalk on nominal delays and delay uncertainty are examined Effects of crosstalk on nominal delays and delay uncertainty are examined Monotonic ordering according to driver strength is shown to be advantageous for the various objective functions Monotonic ordering according to driver strength is shown to be advantageous for the various objective functions Examples for 90-nanometer technology are analyzed and discussed Examples for 90-nanometer technology are analyzed and discussed

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