1. 1Muhammad Amir Yousaf o Von-Neumann Architecture o Registers o Von Neumann Architecture o Von Neumann SAP o Instruction Set o Instruction execution o Von Neumann Architecture’s limitation o Harvard Architecture LECTURE 1

2. 2Muhammad Amir Yousaf The Basic Register o A register is a storage device that is capable of holding the collection of one or more bits. 0 0 1 1.... n-1 N bit Register D0D0 D n-1 D0D0 Clk R,/W En

3. 3Muhammad Amir Yousaf Data Transfer between registers 0 0 1 1.... n- 1 D0D0 D n-1 Clk R 2,/W 2 En 2 0 0 1 1.... n- 1 D0D0 D n-1 Clk R 1, /W 1 En 1 Control Signal 1 1 1 0

4. 4Muhammad Amir Yousaf CPUCPU Memory Output Register Execution unit ALU Control unit IR Controller System bus Both data and instructions at the same system bus MAR Register B Register A Binary Display PC VON NEUMANN ARCHITECTURE

5. 5Muhammad Amir Yousaf CPU RAM 16 x 8 Output Register ALU Controller MAR Register B Register A Binary Display PC IR Clk clr EpEp CpCp LmLm Clk CE clr LiLi EiEi EaEa LaLa LbLb S E Lo Clk clr E p C p E i L i E a L a S E L b L m CE Lo VON NEUMANN SAP Simple As Possible Computer

6. INSTRUCTION SET  The instruction set specifies the basic operations supported by the machine.  It provides an interface to the underlying hardware.  It expresses the machine’s ability to transfer data, store data, operate on data and make decisions. Components in a microprocessor system 6 Muhammad Amir Yousaf o Arithmetic and Logic Instruction. o Looping and decision making. o Transfer of data. o Transfer of control.

7. INSTRUCTION SET Components in a microprocessor system 7 Muhammad Amir Yousaf  The entities that instructions operate on are denoted operands.  The number of operands that an instruction operate on is called arity of operation. ADD 9H ADD R1,R2 z = x+y; x = x+y; x++;

8. INSTRUCTIONS 8Muhammad Amir Yousaf More on Operand 0 (Source and/or Destination) Operand 0 (Source and/or Destination) Operation 15 x 0 Operation 15 x 0 Operand 0 Source Operand 0 Source Operand 1 Src / Destination Operand 1 Src / Destination Operation 15 x 0 Operand 2 Src / Dest Operand 2 Src / Dest Operand 1 Src Operand 1 Src Operand 0 Src Operand 0 Src o The size of operation field is determined by the number of instructions a machine supports. o Each instruction is given a unique code called op-code

9. INSTRUCTION SET FOR SAP Components in a microprocessor system 9 Muhammad Amir Yousaf InstructionOperation 000Load RAM data into Register A 001Add RAM data to RegisterA 010Subtract RAM data from RegisterA 011Load RegisterA into Output register 111Stop Processing

10. INSTRUCTION SET  These numbers, called op-codes can be stored in program memory and can be fetched by the computer during execution.  Mnemonic names are given to op-code’s binary pattern to make them easier to work with. Components in a microprocessor system 10Muhammad Amir Yousaf MnemonicsOp-codesOperation LDA0000Load RAM data into Register A ADD0001Add RAM data to RegisterA SUB0010Subtract RAM data from RegisterA OUT0011Load RegisterA into Output register HLT1111Stop Processing  Assembler translate these mnemonics to op-codes

11. INSTRUCTION SET  LDA instruction includes the hex address of the data to be loaded. LDA 8H  ADD instruction includes the address of the word to be added into RegisterA. ADD 9H means ‘add the contents of memory location 9H to the RegisterA’; the sum replaces the original contents of RegisterA  SUB instruction includes the address of the word to be subtracted.  RegisterB holds the word to be operated, adder/sub compute instantly and the result is written on RegisterA. Components in a microprocessor system 11Muhammad Amir Yousaf

12. PROGRAMMING SAP Components in a microprocessor system 12Muhammad Amir Yousaf AddressMnemonics 0HLDA 9H 1HADD AH 2HADD BH 3HSUB CH 4HOUT 5HHLT AddressData 6HFFH 7HFFH 8HFFH 9H01H AH04H BH02H CH03H DHFFH EHFFH FHFFH How instructions are stored in the memory? Assembly language: language of mnemonics Machine language : language of 1,0 strings 0H:0000 1001

13. 13Muhammad Amir Yousaf CPU RAM 16 x 8 Output Register ALU Controller MAR Register B Register A Binary Display PC IR Clk clr EpEp CpCp LmLm Clk CE clr LiLi EiEi EaEa LaLa LbLb S E Lo Clk clr E p C p E i L i E a L a S E L b L m CE Lo ADDRESSES o Each location in memory has an associated address. o Information is accessed in memory by giving that. o If a memory has 16 locations, it will have 16 addresses. o Address word size to access all the locations? MSB N-1 0 MSB N-1 0 Big Endian Little Endian

14. 14Muhammad Amir Yousaf CPU Output Register ALU Controller Register B Register A Binary Display PC IR Clk clr EpEp CpCp LmLm Clk CE clr LiLi EiEi EaEa LaLa LbLb S E Lo Clk clr E p C p E i L i E a L a S E L b L m CE Lo PC MAR PC  MAR INSTRUCTION EXECUTION CYCLE Fetch instr. RAM 16x8

15. 15Muhammad Amir Yousaf CPU Output Register ALU Controller Register B Register A Binary Display PC IR Clk clr EpEp CpCp LmLm Clk CE clr LiLi EiEi EaEa LaLa LbLb S E Lo Clk clr E p C p E i L i E a L a S E L b L m CE Lo PC MAR Instruction Execution Cycle Fetch instr. PC Inc RAM 16x8

16. 16Muhammad Amir Yousaf CPU Output Register ALU Controller Register B Register A Binary Display PC Clk clr EpEp CpCp LmLm Clk CE clr LiLi EiEi EaEa LaLa LbLb S E Lo Clk clr E p C p E i L i E a L a S E L b L m CE Lo PC MAR IR 0000 1001 0H:0000 1001 Instruction Execution Cycle Fetch instr. Mem  IR RAM 16x8

17. 17Muhammad Amir Yousaf CPU Output Register ALU Controller Register B Register A Binary Display PC Clk clr EpEp CpCp LmLm Clk CE clr LiLi EiEi EaEa LaLa LbLb S E Lo Clk clr E p C p E i L i E a L a S E L b L m CE Lo PC MAR IR 0000 0H:010 1001 Instruction Execution Cycle Fetch instr.Decode instr. 1001 RAM 16x8 1001

18. 18Muhammad Amir Yousaf CPU Output Register ALU Controller Register B Binary Display PC Clk clr EpEp CpCp LmLm Clk CE clr LiLi EiEi EaEa LaLa LbLb S E Lo Clk clr E p C p E i L i E a L a S E L b L m CE Lo PC MAR IR 0000 0H:010 1001 Instruction Execution Cycle Fetch instr.Decode instr. 1001 RAM 16x8 00000001 Fetch operand 00000001 0000000100000001 Register A

19. 19Muhammad Amir Yousaf CPU Output Register ALU Controller Register B Binary Display PC Clk clr EpEp CpCp LmLm Clk CE clr LiLi EiEi EaEa LaLa LbLb S E Lo Clk clr E p C p E i L i E a L a S E L b L m CE Lo PC MAR IR 0000 0H:010 1001 Instruction Execution Cycle Fetch instr.Decode instr. 1001 RAM 16x8 00000001 Fetch operand 00000001 0000000100000001 Register A ExecuteWrite result

20. DATA TRANSFER INSTRUCTIONS  Responsible for moving data around inside the processor.  Bringing data in from outside and sending data out.  Each data transfer instruction has three pieces of information: o The data o The source o The destination.  The source and destination can be: o A register o Memory o IO port  The path to actual selection of operands is controlled by ‘addressing mode’ specified by operand. 20Muhammad Amir Yousaf

21. DATA TRANSFER INSTRUCTIONS  A portion of each operand field is designated as specification to the hardware as how to interprete the information in the remaining bits of operand fields.  A microprocessor design implements four to eight addressing modes.  Common addressing modes are: o Immediate o Direct and Indirect o Register Direct and Register Indirect o Indexed o Program counter Relative. 21Muhammad Amir Yousaf

22. o Direct and Indirect DATA TRANSFER INSTRUCTIONS o Immediate 22Muhammad Amir Yousaf o Register Direct and Register Indirect  Common addressing modes are:

23. DATA TRANSFER INSTRUCTIONS o Indexed 23Muhammad Amir Yousaf o Program counter Relative  Common addressing modes are:

24. VON NEUMANN LIMITATION  The shared bus between the program memory and data memory leads to the Von Neumann bottleneck.  Because program memory and data memory cannot be accessed at the same time, throughput is much smaller than the rate at which the CPU can work.  The CPU is continuously forced to wait for needed data to be transferred to or from memory.  For example if we try to read an operand at the same time as we try to read an instruction. This is not possible in the von Neumann architecture since we only have one system bus and cannot address two memory positions simultaneously. 24Muhammad Amir Yousaf

25. HARVARD ARCHITECTURE Other Architectures  In the Harvard architecture this is solved by having two separate system buses: o One for instructions o One for data o Data and instructions can be loaded simultaneously, which improves the efficiency.  Means more I/O signals. o More expensive processor. o Uses more power.  Is used internally in modern 32-bit microprocessors and RISC processors. Program Memory CPU Computer Memory I Os Program system Bus Data system Bus 25Muhammad Amir Yousaf

26. MICROPROCESSOR SYSTEM DESIGN 26Muhammad Amir Yousaf General Purpose Computer e.g PC A general-purpose computer, such as a personal computer (PC), is designed to be flexible and to meet a wide range of end-user needs. Embedded Systems An embedded system is designed and optimized to perform a specific task very efficiently. They are different in: o Resources o Real time. o Robustness o Outer world interaction (IOs) o Program structure

27. MICROPROCESSOR SYSTEM DESIGN 27Muhammad Amir Yousaf Embedded Systems An embedded system is designed and optimized to perform a specific task very efficiently. Microprocessor based systems: A microprocessor is an integrated implementation of central processing unit portion (CPU). Use separate integrated circuits for memory and peripherals.

28. MICROPROCESSOR SYSTEM DESIGN 28Muhammad Amir Yousaf Embedded Systems An embedded system is designed and optimized to perform a specific task very efficiently. Microcontroller based systems: A microcontroller brings together a microprocessor core and a rich collection of peripherals and IO capability into single integrated circuit. Reduces cost and size. Timers, ADC, DAC, DIO, serial and parallel communication channels, DMA

29. INSTRUCTION ADDRESSING MODES 29Muhammad Amir Yousaf Instruction Architecture Opcode 03154 Instruction: Add with register Opcode : 0011 or 3 Operand : address of memory location, register or constant Operand1 Operand2 RISC vs CISC Addressing modes

30. PROCESSOR TYPES:  CISC (Complex Instruction Set Computer) o The primary goal of CISC architecture is to complete a task in as few lines of assembly as possible. o This is achieved by building processor hardware that is capable of understanding and executing a series of operations. o "MULT“. When executed, this instruction loads the two values into separate registers, multiplies the operands in the execution unit, and then stores the product in the appropriate register. Thus, the entire task of multiplying two numbers can be completed with one instruction: o MULT 2:3, 5:2 Components in a microprocessor system 30Muhammad Amir Yousaf

31. REDUCED INSTRUCTION SET COMPUTING  RISC (Reduced Instruction Set Computer) o RISC processors only use simple instructions that can be executed within one clock cycle. o Thus, the "MULT" command described above could be divided into three separate commands: o LOAD, which moves data from the memory bank to a register, o PROD, which finds the product of two operands located within the registers. o STORE, which moves data from a register to the memory banks. o A programmer would need to code four lines of assembly: Components in a microprocessor system 31Muhammad Amir Yousaf LOAD A, 2:3 LOAD B, 5:2 PROD A, B STORE 2:3, A

32. MEMORY:  To store data or instructions the computer system uses a so- called primary memory  The executable program code and data is stored in main memory.  The primary memory is divided in two main parts o RAM o ROM The memory can be seen as a number of post boxes Components in a microprocessor system 32Muhammad Amir Yousaf

33. MICROCONTROLLERS What does a computer system comprise: o Processor (CPU, Central Processing Unit) o Memory o Peripheral units, I/O o System bus, to communicate with peripheral units If we have a chip that comprise all this it is often called a ‘Micro Controller’ The outer world/ The user I/O unit RAM ROM Primary Memory CPU Von Neumann Architecture 33Muhammad Amir Yousaf

34. PROCESSOR SYSTEM BUS  Data bus o Communication channel to move data to and from CPU and peripheral units.  Address bus o Used to point out which memory position or IO port that is to be read or written. Components in a microprocessor system 34Muhammad Amir Yousaf  Control signals o Used to signal when a data transaction starts and stops. o For example signals if a transaction is a read or write operation.

35. REFERENCES  Lecture slides: Benny Thörnberg, Mattias O’ Nils  Video Lecture: Prof. Anshul Kumar  http://www.computersciencelab.com/ComputerHistory/History.htm  Webopedia  http://www.world-war-2-planes.com/american-world-war-2-planes.html (slide 12) http://www.world-war-2-planes.com/american-world-war-2-planes.html  http://www.anvari.org/cols/Typewritter_ASCII_Art/Steam_Engine_Number_3.html (slide 10) http://www.anvari.org/cols/Typewritter_ASCII_Art/Steam_Engine_Number_3.html  http://www.old-computers.com/history/detail.asp?n=61 (slide 15) http://www.old-computers.com/history/detail.asp?n=61  http://www.freewebs.com/computingstudies/S1_UT_Systems/S1UTSystems_07.ht m http://www.freewebs.com/computingstudies/S1_UT_Systems/S1UTSystems_07.ht m  http://www.computer-museum.org/index.html http://www.computer-museum.org/index.html  http://www.ucdsb.on.ca/school/sla/aboutus/Pages/ExamSchedule.aspx http://www.ucdsb.on.ca/school/sla/aboutus/Pages/ExamSchedule.aspx  http://www.youtube.com/watch?v=AqbyMRs3ocs http://www.youtube.com/watch?v=AqbyMRs3ocs  Camera Pills Use MEMS Micro Reed Sensors to Activate the Battery  http://en.wikipedia.org/wiki http://en.wikipedia.org/wiki  http://www-cs-faculty.stanford.edu/~eroberts/courses/soco/projects/risc/risccisc/ 35Muhammad Amir Yousaf