1. pc structure Avi Mendelson 6/2005 1 MAMAS – Computer Architecture PC Structure and Peripherals Dr. Avi Mendelson

2. pc structure Avi Mendelson 6/2005 2 The Motherboard

3. pc structure Avi Mendelson 6/2005 3 The Motherboard PCI Bus: 133MB/s = 32bit ×33MHz Monitor L2 Cache CPU FSB 800MHz Graphics Adaptor Video Buff North Bridge DRAM Ctrlr PCI Expan. Slots I/O Controller Floppy Disk Drive Key- board Speakers Sound Card Hard Disk Drive CD ROM Drive South Bridge IDE Ctrlr AGP×8 Memory Memory Bus Parallel PortSerial Port Modem Phone Line Network card USB Ctrlr Hub interface LCP SATA Ctrlr Hard Disk Drive PS2 mouse USB mouse

4. pc structure Avi Mendelson 6/2005 4 Motherboard Chipset Processor

5. pc structure Avi Mendelson 6/2005 5 SRAM vs. DRAM  Random Access: access time is the same for all locations  DRAM: Dynamic RAM – used for main memory – High density, low power, cheap, slow – Dynamic: need to be “refreshed” regularly (~1% time) – Typical usage: main memory – Address divided into 2 halves (2D matrix memory): row and column – Not really “Random Access”: penalty when accessing new row (page)  SRAM: Static RAM – used for caches, – Low density, high power, expensive, fast – Static: content lasts “forever” (until lose power) – Typical usage: cache – No refresh (6 transistors/bit vs. 1 transistor/bit) – Address not multiplexed  DRAM/SRAM Size 32 : 1 (512:16)  SRAM/DRAM latency 8 : 1 (30:3.5)

6. pc structure Avi Mendelson 6/2005 6 CapacitySpeed Logic2× in 3 years2× in 3 years DRAM4× in 3 years1.4× in 10 years Disk2× in 3 years1.4× in 10 years Technology Trends CPU-DRAM Memory Gap (latency)

7. pc structure Avi Mendelson 6/2005 7 Row latch Row address decoder Column latch Column address decoder CAS# RAS# DATA Memory array Memory address bus Basic DRAM chip  Addressing sequence  Row address and then RAS# asserted  RAS# to CAS# delay  Column address and then CAS# asserted  DATA transfer

8. pc structure Avi Mendelson 6/2005 8 Basic SDRAM controller DRAM address decoder Time delay gen. address mux RAS# CAS# R/W# A[20:23] A[10:19] A[0:9] Memory address bus D[0:7] Select Chip select  DRAM data must be periodically refreshed – Needed to keep data correct – DRAM refresh is done by the DRAM controller, using refresh counter

9. pc structure Avi Mendelson 6/2005 9 DIMMs  DIMM: Dual In-line Memory Module – A small circuit board that holds memory chips  64-bit wide data path (72 bit with parity) – Single sided: 9 chips, each with 8 bit data bus  512 Mbit / chip  8 chips  512 Mbyte per DIMM – Dual sided: 18 chips, each with 4 bit data bus  256 Mbit / chip  16 chips  512 Mbyte per DIMM

10. pc structure Avi Mendelson 6/2005 10 Read Only Memory (ROM)  Random Access  Non volatile  PROM – Programmable ROM – Burnt once using special equipment  EPROM – Erasable PROM – Can be erased by exposure to UV, and then reprogrammed  E2PROM – Electrically Erasable PROM – Can be erased and reprogrammed on board – Write time (programming) much longer than RAM – Limited number of writes (thousands)

11. pc structure Avi Mendelson 6/2005 11 Flash Memory  Non-volatile, rewritable memory – limited lifespan of around 100,000 write cycles  Flash drives compared to HD drives: – Smaller size, faster, lighter, noiseless, consume less energy – Withstanding shocks up to 2000 Gs  Equivalent to a 10 foot drop onto concrete - without losing data – Much lower capacity (around 100MB) – Much more expensive (cost/byte)

12. pc structure Avi Mendelson 6/2005 12 Chipset Example – Intel ® 875P North – fast connection to memory/CPU South – Slow connection to memory/CPU

13. pc structure Avi Mendelson 6/2005 13 Hard Disk

14. pc structure Avi Mendelson 6/2005 14 Hard Disk Structure  Direct access  Nonvolatile, Large, inexpensive, and slow – Lowest level in the memory hierarchy  Technology – Rotating platters coated with a magnetic surface – Use a moveable read/write head to access the disk – Each platter is divided to tracks: concentric circles – Each track is divided to sectors  Smallest unit that can be read or written – Disk outer parts have more space for sectors than the inner parts  Constant bit density: record more sectors on the outer tracks  speed varies with track location  Buffer Cache – A temporary data storage area used to enhance drive performance Platters Track Sector

15. pc structure Avi Mendelson 6/2005 15 The IBM Ultrastar 36ZX  Top view of a 36 GB, 10,000 RPM, IBM SCSI server hard disk  10 stacked platters

16. pc structure Avi Mendelson 6/2005 16 Disk Access Read/write data is a three-stage process  Seek time: position the arm over the proper track – Average: Sum of the time for all possible seek / total # of possible seeks – Due to locality of disk reference, actual average seek is shorter – 4 to 12 ms  Rotational latency: wait for desired sector to rotate under head – The faster the drives spins, the shorter the rotational latency time – Most disks rotate at 5,400 to 15,000 RPM  At 7200 RPM: 8 ms per revolution – An average latency to the desired information is halfway around the disk  At 7200 RPM: 4 ms  Transfer block: read/write the data – Transfer Time is a function of:  Sector size  Rotation speed  Recording density: bits per inch on a track – Typical values: 100 MB / sec  Disk Access Time = Seek time + Rotational Latency + Transfer time +Controller Time + Queuing Delay

17. pc structure Avi Mendelson 6/2005 17 Disk Performance (mean value analysis)  Avg. disk access = – avg. seek time – + avg. rot. delay – + transfer time – + overhead  Example: – 5400 RPM; 5 MB/sec – Avg. seek time: 9 ms – Controller overhead:.5 ms – Time to read 4K byte block = 9 ms +.5/5400rpm + 4KB/5 MB/sec +.5 ms = 9 ms + 5.6ms +.8 ms +.5 ms = 16.9 ms

18. pc structure Avi Mendelson 6/2005 18 Performance evaluation using (simple) Queuing Theory rules ­ More interested in long term, steady state than in startup => Arrivals = Departures ­ Little’s Law: Mean number tasks in system = arrival rate x mean response time Observed by many, Little was first to prove ­ Applies to any system in equilibrium, as long as nothing in black box is creating or destroying tasks ArrivalsDepartures

19. pc structure Avi Mendelson 6/2005 19 A Little Queuing Theory: Notation ­ Queuing models assume state of equilibrium: input rate = output rate ­ Notation: r average number of arriving customers/second T ser average time to service a customer (tradtionally µ = 1/ T ser ) userver utilization (0..1): u = r x T ser (or u = r / T ser ) T q average time/customer in queue ≈ Tser x u / (1 – u) T sys average time/customer in system: T sys = T q + T ser L q average length of queue: L q = r x T q L sys average length of system: L sys = r x T sys ­ Little’s Law: Length system = rate x Time system (Mean number customers = arrival rate x mean service time) ProcIOCDevice Queue server System

20. pc structure Avi Mendelson 6/2005 20 A Little Queuing Theory: An Example ­ processor sends 40 x 8KB disk I/Os per second, requests & service exponentially distrib., avg. disk service = 20 ms ­ On average, how utilized is the disk? What is the number of requests in the queue? What is the average time spent in the queue? What is the average response time for a disk request? ­ Notation: raverage number of arriving customers/second = 40 T ser average time to service a customer = 20 ms (0.02s) userver utilization (0..1): u = r x T ser = 40/s x.02s = 0.8 T q average time/customer in queue = T ser x u / (1 – u) = 20 x 0.8/(1-0.8) = 20 x 4 = 80 ms (0.08s) T sys average time/customer in system: T sys =T q +T ser = 100 ms = 0.1 s L q average length of queue:L q = r x T q = 40/s x.08s = 3.2 requests in queue L sys average # tasks in system: L sys = r x T sys = 10/s x.1s = 1

21. pc structure Avi Mendelson 6/2005 21 A Little Queuing Theory: Example 2 ­ processor sends 40 x 8KB disk I/Os per second, requests & service exponentially distrib., avg. disk service = 10 ms ­ On average, how utilized is the disk? What is the number of requests in the queue? What is the average time spent in the queue? What is the average response time for a disk request? ­ Notation: raverage number of arriving customers/second = 40 T ser average time to service a customer = 10 ms (0.01s) userver utilization (0..1): u = r x T ser = 40/s x.01s = 0.4 T q average time/customer in queue = T ser x u / (1 – u) = 10 x 0.4/(1-0.4) = 10 x 0.667 =~ 6.7 ms (0.0067s) T sys average time/customer in system: T sys =T q +T ser = 16.7 ms L q average length of queue:L q = r x T q = 40/s x.0067s = 0.27 requests in queue L sys average # tasks in system: L sys = r x T sys = 40/s x.025s = 0.67

22. pc structure Avi Mendelson 6/2005 22 A Little Queuing Theory: Conclusion  Disk utilization must be kept low – But only for the random model

23. pc structure Avi Mendelson 6/2005 23 Disk optimizations  Locality – Disks exhibit locality just like main memories – In “local access environment”, seek is diminished to 1/3  Disk layout – Optimal layout of data for sequential data access – Using tools such as “defragmentation” for better data layout  Caching – Done in main memory – And in Disk Drive  Latency reduced to hit overhead plus transfer  Scheduling – OS based schedule of requests

24. pc structure Avi Mendelson 6/2005 24 The Disk Interface – EIDE  EIDE, ATA, UltraATA, ATA 100, ATAPI: all the same interface – Uses for connecting hard disk drives and CD-ROM drives – 80-pin cable, 40-pin dual header connector – 100 MB/s (ATA66 is only 66MB/s) – EIDE controller integrated with the motherboard (in the ICH)  EIDE controller has two channels: primary and a secondary – Work independently – Two devices per channel: master and slave, but equal  The 2 devices have to take turns controlling the bus  A total of four devices per cont – If there are two device on the system (e.g., a hard disk and a CD-ROM)  It is better to put them on different channels – Avoid mixing slower (CD) and faster devices (HDD) on the same channel – If doing a lot of copying from a CD-ROM drive to the CD-RW  Better performance by separating devices to separate channels

25. pc structure Avi Mendelson 6/2005 25 The Disk Interface – Serial ATA (SATA)  Point-to-point connection – Ensures dedicated 150 MB/s per device (no sharing)  Dual controllers allow independent operation of each device  Thinner (7 wires), flexible, longer cables – Easier routing and improved airflow – 4 wires for signaling + 3 ground wires to minimize impedance and crosstalk  New 7-pin connector design – for easier installation and better device reliability – takes 1/6 the area on the system board  CRC error checking on all data and control information  Increased BW supports data intensive applications such as – digital video production, digital audio storage and recording, high-speed file sharing  No configuration needed when a adding a 2 nd SATA drive – One cable for each drive eliminates the need for jumpers – No more figuring out which device is the master or slave  Today's hard drives are clearly below 100 MB/s – Do not benefit from UltraATA / SATA

26. pc structure Avi Mendelson 6/2005 26 The Disk Interface – SCSI  Small Computer System Interface  SCSI hard disks are more expensive than EIDE hard disks  SCSI requires an extra controller, connected to the PCI bus  In a standard environment, the performance of single hard disk won’t improve much from the SCSI interface  The power of SCSI is that several devices can use the bus at the same time, not using the bus while they don’t need it  The best benefit from SCSI is when several devices are all used on the same bus

27. pc structure Avi Mendelson 6/2005 27 Some Disk Examples sizeGB40 80 36.4 Platter Rotational SpeedRPM54007200 15K InterfaceATA SATASCSI Average Latencyms5.64.2 4.72 Average Seek Timems129993.6 Number of palters11112 Cache SizeMB22288 Max Transfer RateMBps100 24086 Max Transfer Rate (Burst)MBps100 320 Sustained Lowest Transfer RateMBps20 23 57 Sustained Highest Transfer RateMBps323542 76 Sizeinch3.5

28. pc structure Avi Mendelson 6/2005 28 RAID RAID 0 (Striping)RAID 1 (Data Mirror) Customer Sees:2x120GB = 240GB120GB System: CharacteristicsRAID controller breaks data to blocks; distributes pieces to both drives RAID controller writes the same data to both drives Customer Benefit Offers performance benefits over a single hard drive configuration Offers data integrity: if one drive fails, data is still intact on the other drive High performance and capacity for storage intensive applications Failsafe storage, while increasing read performance

29. pc structure Avi Mendelson 6/2005 29 CDROM / DVD Drive  Read speed (max) – Compared to the speed of an audio CD or a video DVD  Write speed  Re-write speed  Capacity 700MB(CD), 4.7GB (DVD)  Interface: EIDE/ATAPI  Data transfer rate (max): – CD 48x : 7.2MB/s = 153,600B/s x 48 – DVD 16x: 21MB/s = 1,250,000B/s x 16  CD-R: CD-Recordable: can be written once  CD-RW: CD-ReWritable: can be written/erased many times (up to 1000)

30. pc structure Avi Mendelson 6/2005 30 BackUp

31. pc structure Avi Mendelson 6/2005 31 3 rd Generation Local I/O bus Requirements  Supports multiple market segments and emerging applications: – Unified I/O Architecture for Desktop, Mobile, Server, Communications Platforms, Workstations and Embedded Devices  Low cost and high volume – Cost at or below PCI cost structure at the system level  PCI Compatible software model – Boot existing operating systems without any change – PCI compatible configuration and device driver interfaces  Performance: – Scalable performance via frequency and additional lanes – High Bandwidth per Pin. Low overhead. Low latency.  Support multiple platform connection types – Chip-to-chip, board-to-board via connector, docking station and enable new form factors  Advanced features – Comprehend different data types. Power Management. Quality Of Service. Hot Plug and Hot Swap support. Data Integrity and Error Handling. Extensible. Base mechanisms to enable Embedded and Communications applications.  Non-Goals – Coherent interconnect for processors, memory interconnect, cable interconnect for cluster solutions.

32. pc structure Avi Mendelson 6/2005 32 DRAM Standards LabelNameEffective Clock RateData BusBandwidth PC66SDRAM66 MHz64 Bit0,5 GB/s PC100SDRAM100 MHz64 Bit0,8 GB/s PC133SDRAM133 MHz64 Bit1,06 GB/s PC1600DDR200100 MHz64 Bit1,6 GB/s PC1600DDR200 Dual100 MHz2 x 64 Bit3,2 GB/s PC2100DDR266133 MHz64 Bit2,1 GB/s PC2100DDR266 Dual133 MHz2 x 64 Bit4,2 GB/s PC2700DDR333166 MHz64 Bit2,7 GB/s PC2700DDR333 Dual166 MHz2 x 64 Bit5,4 GB/s PC3200DDR400200 MHz64 Bit3,2 GB/s PC3200DDR400 Dual200 MHz2 x 64 Bit6,4 GB/s PC4200DDR533266 MHz64 Bit4,2 GB/s PC4200DDR533 Dual266 MHz2 x 64 Bit8,4 GB/s PC800RDRAM Dual400 MHz2 x 16 Bit3,2 GB/s PC1066RDRAM Dual533 MHz2 x 16 Bit4,2 GB/s PC1200RDRAM Dual600 MHz2 x 16 Bit4,8 GB/s PC800RDRAM Dual400 MHz2 x 32 Bit6,4 GB/s PC1066RDRAM Dual533 MHz2 x 32 Bit8,4 GB/s PC1200RDRAM Dual600 MHz2 x 32 Bit9,6 GB/s

33. pc structure Avi Mendelson 6/2005 33 RDRAM  Developed by Rambus  Designed to achieve high bandwidth with a low pin count – 2 byte data + 1 byte control for the entire “channel”  High frequency (800MHz)  Complex architecture  Typical 64MByte RDRAM-D Memory configuration: Memory Controller Data Control /8 /16 64Mbit RDRAM-D RDRAMRDRAM RDRAMRDRAM RDRAMRDRAM RDRAMRDRAM RDRAMRDRAM RDRAMRDRAM RDRAMRDRAM RDRAMRDRAM 16 Bank/Device Architecture