# Number Representation and Logic Design CS 3220 Fall 2014 Hadi Esmaeilzadeh Georgia Institute of Technology Some slides adopted from.

## Presentation on theme: "Number Representation and Logic Design CS 3220 Fall 2014 Hadi Esmaeilzadeh Georgia Institute of Technology Some slides adopted from."— Presentation transcript:

Number Representation and Logic Design CS 3220 Fall 2014 Hadi Esmaeilzadeh hadi@cc.gatech.edu Georgia Institute of Technology Some slides adopted from Prof. Milos Prvulovic

Computing with digital technology  Physical Layer – Low voltage (0 V) – High voltage (5 V, then 3.3 V, 1.1 V, and now is 0.9 V or lower)  Abstraction (we do not deal with voltage levels) – ‘0’ – ‘1’  Groups of binary values construct words, numbers, pixels, audio signals, … 2

What does this binary value represent? 01001000011000010110010001101001 = 0100_1000 0110_0001 0110_0100 0110_1001 3

What does this binary value represent? 01001000011000010110010001101001 = 0100_1000 0110_0001 0110_0100 0110_1001 Hadi 1214342249 230801.64 … 4

Terminology  Physical: – Bit: one binary digit  Abstract: – Nibble: four binary digits – Byte: eight binary digits = two nibbles – Word: Usually 32 binary digits = 4 bytes 5

Number Representation  Positional notation Same as base-10 but now it’s base 2: – In base 10, we have 9807 = 9*10 3 + 8*10 2 + 0*10 1 + 7*10 0 – In base 2, we have 1011 = 6

Signed numbers  Easy: one bit for sign, then absolute value – E.g. 1011 (- 011) is actually -3  How do we add two such numbers? – First check the sign bits – If both are 1 or both 0, add the absolute values and retain the same sign bit – If one is 1 and one is 0, compare the two absolute values, then subtract the smaller from the larger and use the sign of the larger number  Lots of circuitry needed for all this!  Also we have to representation for zero: (-0, +0)  We need a better way! 7

Two’s complement  OK, let’s say we want 4-bit signed numbers but – Want to just add the numbers as if they were unsigned – Want to quickly tell if number is positive or negative  So if we add 1 to -1 we should get 0 – 0 is 0000, 1 is 0001, so -1 has to be 1111  Now, if we add 1 to -2, we should get -1 – So -2 has to be 1110  We can still tell if positive or negative  But add, subtract, etc. is much simpler now 8

Two’s complement 9 What is the range?

Two’s complement  Quickly negate a 2’s number: – 1011 – Invert(all bits) + ‘1’ – Start from right, copy until the first ‘1’, then invert the remaining  Sign extension: – Store 1011 in a byte 10

Note on Number Representation  Digital logic still operates on binary signals  2’s complement vs. sign-and-value is all about how we choose to represent numbers using the underlying binary signals  If four wires have values of 1, 0, 1, 1, then – If sign-and-value, it represents -3 – If 2’s complement, it is -5 – If unsigned number, it is 11 (eleven) – May not even be a number! 11

Hexadecimal Notation  Writing binary numbers is inconvenient – More than 3 times as many digit as decimal notation  So we also use hexadecimal (base 16) notation – Fewer digits needed than in binary (or even decimal) – Each hex digit represents exactly 4 binary digits, so it is easy to convert back-and-forth – Example: Hexadecimal E04C is in binary:  Note: no actual “hexadecimal” hardware – Hardware still operates in binary – Hexadecimal notation is only for our convenience 12

Digital Logic  Implemented using MOS transistors 13 P-type substrate N-type Source Gate Drain Channel - - -

MOS transistor 14 +V

Inverter (NOT gate) 15 +V

NOR 16 +V

NAND 17 +V

How do we get AND and OR gates? 18

XOR? 19

Gates with more inputs 20 ?

1-bit add 21 A B OUT Carry OUT

Full Adder 22 A B OUT Carry OUTCarry IN

Full adder 23 A B Cin S (Ouptut) A B Cout

3-bit add? 26 1-bit Full Adder Cin B0A0 S0 Cout 1-bit Full Adder Cin B1A1 S1 Cout 1-bit Full Adder Cin B2A2 S2 Cout Data dependence serializes the additions!

Keeping State 27 We use latches and flip-flops – Here is an SR latch

D latch 28 When E is 1 – When D=1, make the S signal be 0 (OUT -> 1) – When D=0, make the R signal be 0 (OUT -> 0) – When E is 0, both S and R are 1 (OUT unchanged) S R OUT D(ata) E(nable) D (inverted D input)

Flip-Flop?  Essentially two latches in series:  Latch 1 has CLK connected to its “Enable” – Keeps latching changes in input value while clock is 0 – When clock becomes 0, it keeps what it had  Latch 2 has CLK connected to its enable – Keep latching the output of Latch 1 while clock is 1 – Keeps same output value when clock is 0  While clock is 0, Latch 2 outputs the stored bit  When clock becomes 1, Latch 2 outputs 29

How the flip-flop works  While clock is 0 – Output of Latch 1 follows the input – But Latch 2 outputs the stored bit  When clock changes from 0 to 1 – Latch 1 stops following the input – Latch 2 now outputs what Latch 1 is outputting – Result: FF output == FF input when clock went 0->1  When clock changes back to 0 – Latch 1 starts following the input again – But Latch 2 now keeps what it had – Result: FF output unchanged until clock goes 0->1 30